CMP—The Next Fifteen Years

Abstract

In the early 1990s, reports by some IC manufacturers on the use of silicon wafer polishers to reduce the topography in interlevel dielectric (ILD) films created by multiple levels of metallization began to surface. Dismissed at first as irrational, such reports eventually proved to be true as the CMP industry began gaining ground. By the end of the decade, feature densities approaching sub-100 nm demanded not only an ILD CMP but CMP steps in the front end of the line (FEOL) as well. Process designers referred to CMP reverently as an enabling technology because the planarity it afforded was required for submicron lithography and multilevel metallization. But CMP engineers and integrators regarded the new process as more of a necessary evil because of the many challenges associated with controlling the new technology in high volume manufacturing. These conflicting perceptions of CMP as an enabling technology that is difficult to manage have persisted throughout CMP's more than 15 years' history. Table 20.1 shows the technology node and the year in which the manufacturing of key CMP processes was introduced at Intel Corporation. These CMP processes, while enabling different aspects of IC technology, shared several key features. First and foremost, they were all revolutionary technologies in that they (1) significantly advanced in the state of the art, (2) required significant capital investment, and (3) required significant development efforts to make them work. An additional feature that the CMP processes shared was that they were unique solutions as, for most of them, there was no viable alternative to their use-these CMP steps were required.

Novel Probability Density Function of Pad Asperity by Wear Effect over Time in Chemical Mechanical Planarization

“…Semiconductor processing technology has led to decreased transistor sizes and an increased number of integrated transistors, resulting in highly integrated semiconductor devices with high performance [1,2]. To integrate more devices, a multilevel interconnection structure is essential, and a surface planarization process is required for the stable deposition of the layers [3].…”

Origin and Innovations of CMP Slurry

“…Later, this technology was also applied to the semiconductor device manufacturing process. [2][3][4][5] CMP technology has now made it possible to achieve flat and smooth surfaces at the nano-or atomic level. On the other hand, CMP faces many challenges such as: (1) Reducing nano-level defects and contamination, (2) Polishing of a wide variety of difficult-to-process materials, from hard brittle materials to composite materials, and (3) Improving productivity through highly efficient polishing.…”

Using Discrete Wavelet analysis and Sequential test to detect the endpoint in CMP process

“…The abrasive particles come to remove this layer of transformed matter. Joseph et al [1] define three main players in this process, shown in figure 1, presented by: 1. The surface to be polished.…”