A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

Yasutake, N.; Ohuchi, K.; Fujiwara, M.; Adachi, K.; Hokazono, A.; Kojima, Kazunobu; Aoki, Naofumi; Suto, Hirofumi; Watanabe, T.; Morooka, T.; Mizuno, Hiroaki; Magoshi, Shunko; Shimizu, Takashi; Mori, Seiichi; Oguma, H.; Sasaki, Takahiro; Ohmura, M.; Miyano, K.; Yamada, Hitoshi; Tomita, Hidemoto; Matsushita, Daisuke; Muraoka, K.; Inaba, S.; Takayanagi, Motowo; Ishimaru, K.; Ishiuchi, H.

doi:10.1109/vlsit.2004.1345407

Cited by 35 publications

(16 citation statements)

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“…Not only the individual but also the combined effects of RDD, LER, and OTV on the threshold-voltage fluctuations have been studied. Although the expectations are that the conventional MOSFETs will be replaced by ultrathin body SOI or doublegate transistors after the 45-nm technology node, recently, it has been demonstrated experimentally that the cost-efficient bulk MOSFET architecture could be successfully scaled, at an individual device level, to a 10-nm channel length [29].…”

Section: Introductionmentioning

confidence: 99%

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

Roy

Brown

Adamu-Lema

et al. 2006

IEEE Trans. Electron Devices

263

117

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Abstract-In this paper, using three-dimensional statistical numerical simulations, the authors study the intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness (LER), and oxide-thickness variations in realistic bulk MOSFETs scaled to 25, 18, 13, and 9 nm. The scaling is based on a 35 nm MOSFET developed by Toshiba, which has also been used for the calibration of the authors' "atomistic" device simulator. Special attention is paid to the accurate resolution of the individual discrete dopants in the drift-diffusion simulations by introducing density-gradient quantum corrections for both electrons and holes. In the LER simulations, two scenarios have been adopted: In the first one, LER follows the prescriptions of the International Roadmap for Semiconductors; in the second one, LER is kept constant close to the current best values. Combined effects of the different sources of intrinsic parameter fluctuations have also been simulated in the 35 nm reference devices and the results for the standard deviation of the threshold voltage compared to the measured values.

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Section: Introductionmentioning

confidence: 99%

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

Roy

Brown

Adamu-Lema

et al. 2006

IEEE Trans. Electron Devices

263

117

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“…The 500 C RTA thermal budget for ion implantation of the self-aligned [IrO -IrO -Hf]-LaAlO -GOI CMOSFETs did not result in any significant degradation of the subthreshold swing ( mV/decade) and (5 m) in underneath 0.18-m Si MOSFETs. Besides, the thermal budget used here is even lower than that of 10-nm MOSFETs [2] and suitable for further 3-D integration with ultrasmall devices. The thermal budget constrain also makes the 3-D integration of Si-on-insulator (SOI) over interconnect and bottom MOSFETs impossible, because of the high RTA temperature (1000 C-1050 C) required for the ion implantation anneal of the top layer SOI CMOSFETs.…”

Section: Resultsmentioning

confidence: 99%

“…O NE of the biggest challenges for very large-scale integration (VLSI) technology is the ac power consumption [1] caused by the interconnect parasitic capacitance ( ), which becomes a major limit for VLSI ICs beyond the implementation of metal-gates and high-nano-CMOS to solve the dc power in gate leakage [2]. Increasing operational frequency ( ) of circuits with denser interconnects makes the ac power consumption even worse.…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional metal gate-high-/spl kappa/-GOI CMOSFETs on 1-poly-6-metal 0.18-/spl mu/m Si devices

Chin

Liao

et al. 2005

IEEE Electron Device Lett.

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We demonstrate three-dimensional (3-D) self-aligned [IrO 2 -IrO 2 -Hf]-LaAlO 3 -Ge-on-Insulator (GOI) CMOSFETs above 0.18-m Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO 2 -LaAlO 3 -GOI p-MOSFETs and IrO 2 -Hf-LaAlO 3 -GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm 2 Vs respectively, without depredating the underneath 0.18-m Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI. Index Terms-Ge-on-insulator (GOI), LaAlO 3 , metal-gate, MOSFET, three-dimensional (3-D).

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“…With price-sensitive services, lower production cost and possible integrations consumer electronics driving developments, CMOS technology offers the advantages of an accessible foundry with the digital baseband. The present state-of-the art CMOS process nodes at sub-100nm demonstrate device f t that exceeds 400 GHz [6], thereby providing reasonable gain and other design margins for 60 GHz systems. A critical building block in the 60 GHz system is the millimeter-wave receiver, which includes the low-noise amplifier (LNA), down conversion mixer, band-pass filter and variable gain amplifier.…”

Section: Introductionmentioning

confidence: 92%

A 1.2 V and 69 mW 60 GHz Multi-channel Tunable CMOS Receiver Design

Öncü¹

2015

RADIOENGINEERING

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A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

Cited by 35 publications

References 0 publications

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

Three-dimensional metal gate-high-/spl kappa/-GOI CMOSFETs on 1-poly-6-metal 0.18-/spl mu/m Si devices

A 1.2 V and 69 mW 60 GHz Multi-channel Tunable CMOS Receiver Design

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