Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

Roy, G.; Brown, Andrew R.; Adamu-Lema, Fikru; Roy, S.; Asenov, A.

doi:10.1109/ted.2006.885683

Cited by 263 publications

(120 citation statements)

References 36 publications

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“…RDD is typically the dominant statistical variability source in bulk MOSFETs, and has been intensively studied [10]-- [12]. In RDD simulations dopants are randomly assigned to locations in the MOSFET based on the nominal local doping concentration using a rejection technique [13]. The effects of LER and MGG are also studied.…”

Section: Simulation Methodologymentioning

confidence: 99%

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Wang

Brown

Cheng

et al. 2014

Solid-State Electronics

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Abstract-Statistical variability and reliability due to random discrete dopants (RDD), gate line edge roughness (LER), metal gate granularity and N/PBIT associated random charge trapping has limited the progressive scaling of bulk planar MOSFETs beyond the 20--nm technology node. In this paper, their impacts on device figures of merit are studied through comprehensive 3--D simulation. It is found that raised drain--bias can exacerbate threshold--voltage fluctuations, mainly due to LER and RDD. Subthreshold slope (SS) variations resulting from each variation source is studied: RDD and LER generate most of the SS variation and are primarily responsible for its skew. Drain induced barrier lowering (DIBL) is examined against each intrinsic variation source, and RDD and LER are found to cause most of the DIBL variability. The correlation of DIBL with threshold--voltage is fully analysed with respect to each source of statistical variability and reliability. Except for LER, all major sources of variability exhibit de--correlation of DIBL against threshold--voltage.

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Section: Simulation Methodologymentioning

confidence: 99%

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Wang

Brown

Cheng

et al. 2014

Solid-State Electronics

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“…The actual simulations carried out at the base of figure 1 primarily involve using the Glasgow three-dimensional 'atomistic' drift/diffusion (DD) simulator (Roy et al 2006). The DD approach accurately models transistor characteristics in the sub-threshold regime, making it well suited for the study of V T fluctuations.…”

Section: Nanocmos E-infrastructure and Simulation Methodologymentioning

confidence: 99%

Enabling cutting-edge semiconductor simulation through grid technology

Reid

Millar

Roy

et al. 2009

Phil. Trans. R. Soc. A.

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The progressive scaling of complementary metal oxide semiconductor (CMOS) transistors drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the unavoidable statistical variations introduced by scaling to be examined in unprecedented detail. Over 200 000 transistors have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS project and describes the way in which the scientific goals have been reflected in the grid-based e-Infrastructure.

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“…Namely, the increase in integrity narrows the operating range of LSI circuits by increasing the ranges of device-characteristic distributions, 3 while the scaled-down devices themselves encounter a larger variation in their characteristics. [4][5][6][7][8] Accordingly, a considerable number of LSI engineers are currently devoted to variation-tolerant circuit designs or to technologies for reducing the variations.…”

Section: Introductionmentioning

confidence: 99%

Spectral analysis of line edge and line-width roughness with long-range correlation

Hiraiwa

Nishida

2010

Journal of Applied Physics

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Large-scale integrations (LSIs) are facing an ever-growing problem of device variability. One of the origins that cause the variability is line-width roughness (LWR) caused by line edge roughness (LER). Accurate characterization of the LWR plays an essential role in controlling the LWR. To do this, we report a methodology, named the “assembly method,” that enables to analyze LWR statistics beyond the conventional correlation length limit, basing on the previous “patchwork” method and recent discrete power spectral density (PSD) method. The methodology virtually assembles a long line by gathering line segments that are randomly scattered on a single line or equally processed different lines. The virtual lines are repeatedly assembled by randomly changing the combination of the segments and the order of the gathered segments while permitting overlaps of the segments between the assembled lines. Squared Fourier transforms of their widths are averaged over the assembled lines to obtain the PSD. By these steps, the statistical noise, which is inherent to experimental PSDs, is markedly reduced. Furthermore, to extract LWR statistics by comparing experimental and theoretical PSDs, we derived an analytic formula of the assembled-line PSD. In the derivation, the randomness of the segment collections played a key role. The PSDs calculated using the formula almost completely fitted experimental PSDs that were obtained by the assembly method. The parameters used in the best-fitted calculation revealed that the photoresist LWR of this study contained a component that had a correlation length of 2780 nm in addition to the previously reported LWR of 35 nm. The LWR variance of the component accounted for approximately 10% of the total variance. The formula also enabled us to evaluate the accuracy of experimentally obtained averages of widths. We find two distinct features in the PSDs by the assembly method. One is the oscillatory structure that shows up in the case when the correlation length is larger than half the length of the segments. A trace of this structure was actually observed in the experimental PSDs of this study. The other is the spikes that are periodically observed as a function of wave number. The spikes originate from a nonstochastic width variation that exists in all the segments in common. Their intensity is proportional to the number of gathered segments in the assembled lines. Because the spikes are excluded from the analysis, the LWR parameters determined by the assembly method are not affected by the nonstochastic variation, unlike the conventional methods. By all these results, we confirm that the assembly method of this study extends the upper limit of analyzable correlation lengths by a factor of approximately 20 and enhances the accuracy as well. This feature also has a practical significance that the widely observed LWR with a correlation length of approximately 35 nm can be analyzed by the assembly method using a conventional critical-dimension scanning-electron-microscope, without resorting to a specially designed one. Accordingly, the method will be a key tool for investigating LER and LWR in developing and manufacturing LSIs. It will also help analyze other stochastic processes in many research and development settings.

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Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

Cited by 263 publications

References 36 publications

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Enabling cutting-edge semiconductor simulation through grid technology

Spectral analysis of line edge and line-width roughness with long-range correlation

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