C. Millar scite author profile

Abstract-The Z 2 -FET operation as capacitor-less DRAM is analyzed using advanced 2D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28 nm FD-SOI devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z 2 -FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.

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Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability

Millar

Reid

Roy

et al. 2008

IEEE Electron Device Lett.

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Variability Aware Simulation Based Design- Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization

Asenov

Cheng

Wang

et al. 2015

IEEE Trans. Electron Devices

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Planar optical waveguides formed by silver-ion migration in glass

Stewart

Millar

Laybourn

et al. 1977

IEEE J. Quantum Electron.

152

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Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS Technology Double-Gate SOI FinFETs

Wang

Cheng

Brown

et al. 2013

IEEE Trans. Electron Devices

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C. Millar

A Self-Consistent Full 3-D Real-Space NEGF Simulator for Studying Nonperturbative Effects in Nano-MOSFETs

Upconversion pumped green lasing in erbium doped fluorozirconate fibre

Analysis of Threshold Voltage Distribution Due to Random Dopants: A 100 000-Sample 3-D Simulation Study

Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM

Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability

Variability Aware Simulation Based Design- Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization

Planar optical waveguides formed by silver-ion migration in glass

Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS Technology Double-Gate SOI FinFETs

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