Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability

Millar, C.; Reid, D.; Roy, G.; Roy, S.; Asenov, A.

doi:10.1109/led.2008.2001030

Cited by 61 publications

(25 citation statements)

References 7 publications

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“…The randomisation is not purely random but is based on the results of three-dimensional geometrical and quantum physics based simulations [6], [7]. Currently RandomSpice is supplied to collaborators with transistor models representing a 35 nm technology by Toshiba [8]. When using RandomSpice to build up SBCBs, the computation required to achieve acceptable accuracy of statistics estimation is largely reduced compared to traditional MC.…”

Section: Methodsmentioning

confidence: 99%

Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits

Xie

Edwards

2010

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

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Abstract-The intrinsic atomistic variability of nano-scale integrated circuit (IC) technology must be taken into account when analyzing circuit designs to predict likely yield. Monte Carlo (MC) based statistical techniques aim to do this by analysing many randomized copies of the circuit. A major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. The MC analyses required for asynchronous circuits are more difficult than are generally required for clocked circuits because of the more complex timing patterns created by handshaking mechanisms. It is important to reduce the computational complexity of MC analysis required for asynchronous circuits. The use of 'Statistical Behavioural Circuit Blocks (SBCB)' is investigated as a means of reducing the dimensionality of the analysis, and this is combined with an implementation of 'Statistical Blockade' to achieve significant reduction in the computational costs. The reduction in computation time achieved by the more efficient MC analysis is illustrated by statistically analysing several simple handshaking circuits.

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Section: Methodsmentioning

confidence: 99%

Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits

Xie

Edwards

2010

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

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“…The asymmetry in the threshold voltage variation induced by random dopant fluctuation originates from the fact that the number of dopant atoms in the channel region is determined by Poisson's distribution [23,39,40]. In other words, because the threshold voltage of the transistors is related to both the positions of the dopant atoms and the number of dopant atoms, there is a mismatch between the various distributions of threshold voltages (note that the Gaussian distribution only considers the position of dopant atoms).…”

Section: Analytical Modelmentioning

confidence: 99%

Random Dopant Fluctuation (RDF)

Shin

2016

Variation-Aware Advanced CMOS Devices and SRAM

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Following Moore's Law [1], semiconductor industries have doubled the density of transistors in integrated circuits (ICs) every two years. This has rapidly increased the performance of ICs because the degree of integration has grown exponentially. However, below the 1 μm technology node, a serious technical issue was encountered that frustrated further shrinking of the gate pitch, namely, the short channel effect (SCE) [2,3]. The short channel effect brings about other undesirable effects, such as threshold voltage (V TH ) roll off [4-6] and drain-induced barrier lowering (DIBL) [7][8][9]. As the portion of the channel region depleted by the source/drain junction increases as much as the channel length is shortened, the threshold voltage is reduced. In other words, lower gate voltage is required to invert the channel region because a larger part of the channel region is already depleted by the source/ drain-to-channel junctions. The second phenomenon, namely, drain-induced barrier lowering (DIBL), occurs when the source-to-channel potential barrier is affected by the drain bias. If the gate length of metal oxide semiconductor field effect transistors (MOSFETs) is scaled down to such an extent that the energy barrier height at the source-to-channel interface is decreased because of the electric field emanating from the drain region, more electrons can diffuse from the source to the drain over the energy barrier at the source/channel interface. This causes higher off-state leakage current, degraded subthreshold slope, and a lowered threshold voltage. In order to alleviate short channel effects, the channel region of MOSFETs should be sufficiently doped to minimize (i) the depletion charge induced by the source/drain junction, and (ii) the impact of drain bias on the modulation of the height of the energy barrier at the source/channel interface [10]. In very scaled MOSFETs in sub-32 nm technology nodes, the doping concentration in the channel (or the halo doping concentration) is close to 10 18 cm −3 or even higher [11,12].

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“…This uncertainty results in substantial variability in the device threshold voltage, sub-threshold slope and drive current. The most significant variations are caused by atoms near the surface and channel of the device [1,26,33]. Line Edge Roughness (LER) is the deviation in the horizontal plane of a fabricated feature boundary from its ideal form.…”

Section: Intrinsic Parameter Fluctuationsmentioning

confidence: 99%

The evolution of standard cell libraries for future technology nodes

Walker

Hilder

Reid

et al. 2011

Genet Program Evolvable Mach

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Evolvable Hardware has been a discipline for over 15 years. Its application has ranged from simple circuit design to antenna design. However, research in the field has often been criticised for not addressing real world problems. Intrinsic variability has been recognised as one of the major challenges facing the semiconductor industry. This paper describes an approach that optimises designs within a standard cell library by altering the transistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm to optimise the device widths within a standard cell. The designs are analysed using statistically enhanced transistor models (based on 3D-atomistic simulations) and statistical SPICE simulations. The goal is to extract high-speed and low-power designs, which are more tolerant to the random fluctuations present in current and future technology nodes. The results

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Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability

Cited by 61 publications

References 7 publications

Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits

Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits

Random Dopant Fluctuation (RDF)

The evolution of standard cell libraries for future technology nodes

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