Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS Technology Double-Gate SOI FinFETs

A Device-Level Characterization Approach to Quantify the Impacts of Different Random Variation Sources in FinFET Technology

“…In order to confirm the above speculations, 'atomistic' TCAD simulations are carried out based on 14nm FinFET template designed in collaboration between IBM, Glasgow University and Gold Standard Simulations (GSS) [10] …”

Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability

“…Simultaneously unavoidable statistical variability exists in nanometer scale transistors, which derives from the discreteness of charge and granularity of matter arising from sources of statistical variability such as random discrete dopants (RDD), gate and fin line-edge-roughness (GER and FER), metal gate granularity (MGG) (Fig.1). In order to well understand the role of longrange process variation, statistical variability and the interaction between them, a design of experiments (DoE) approach has been adopted including the impact of the systematic process variations of gate-length, fin-width and finheight on FinFET characteristics [5]. In this DoE space the CD values deviating from the nominal by several nanometers are listed in Table I, and devices corresponding to the Cartesian product of these CD variations are simulated using GARAND.…”

“…2). Consequently the classic Pelgrom's law scaling of variability with gate area does not hold anymore [5]. This presents a significant challenge to modelling variability at the circuit level and a novel variability modelling methodology is required [13].…”

“…There is also a new source of statistical variability, fin edge roughness (FER), arising from stochastic local variations in the fin patterning [1] [4], which can significantly affect thin body depletion and quantum confinement [1]. It is shown that in FinFETs there is a strong interplay between the statistical variability and the processinduced variability [5], causing additional complications. The variability is challenging for circuit design which requires trade off on performance and power.…”

Variability-aware compact model strategy for 20-nm bulk MOSFETs

“…The channel is doped with a concentration of ~5/3×10 18 cm -3 respectively for n-/p-channel device, and source/drain regions are doped with peak concentration of 3×10 20 cm -3 and the extension regions have a peak density of ~4×10 19 cm -3 . The device structure and doping profiles were transferred to the GSS atomistic simulator Garand [7], which was employed for physical simulations of the interplay between process and statistical variability [8]. Details on the interface are being published elsewhere [9].…”