14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide

Abstract

High performance 14 nm gate length CMOSFETs are demonstrated in this paper. To acquire shallow sourcddrain ( S D ) extension profile, the optimization of low thermal budget process utilizing poly-SiGe and Ni salicide is performed. A poly-SiGe gate electrode minimizes gate depletion effect, therefore high level of dopant activation in the gate electrode is realized even by low temperature spike annealing. Moreover, short channel characteristics are optimized by using offset spacer beside the gate electrode. The highest drive current is achieved in 14 nm gate length CMOSFETs reported to date.

Role of scattering in nanotransistors

“…The significant advances in lithography have led to the construction of nanotransistors with channel lengths smaller than 25 nanometers (nm) [1], [2], [3]. It is believed that devices with channel lengths equal to 10 nm may become possible in research laboratories [4].…”

Investigating the Interfacial Properties of Hf-based/Si and SiO2/Si Gate Stacks

“…This implies that the shift of Hf4f peaks to higher binding energy relative to polycrystalline Hf due to the formation of Hf-OSi bonding at the interface of HfO 2 and bulk Si. The high-k material such as HfO 2 has been reported to be vulnerable to the diffusion of oxygen which causes formation of interfacial layer [6]. But, for HfSiO (figure 4), the Hf4f peaks exhibit no difference with PDA temperature.…”

Low Resistance Electrical Layer Formation: A Simulation Study of Diffusive Rapid Thermal Process on Implanted Dopant Species for Electronics Active Devices

“…Low energy ion implantation is the most popular technique used at present to fabricate ultra shallow junctions. But as an advanced technology, this technique unable to reduce its limitations such as damage to crystal and transiently enhanced diffusion upon annealing this damage [2,5]. Since crystal structure is damaged, there is an effect to junction depth [6,7].…”