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This paper presents the design of a high The forward transform block uses three different throughput multitransform and multiparallelism IP for transforms, depending on the type of input data. This H.264/AVC standard. This solution supports the five transforms are 4x4 FDCT, 4x4 forward Hadamard and 2x2 H.264/AVC transforms and it supports five different levels of forward Hadamard. The inverse transform block is also parallelism. The proposed architecture were described in formed by three different transforms: 4x4 IDCT, 4x4 inverse VHDL and synthesized to Altera Stratix and Xilinx Virtex-It Hadamard and 2x2 inverse Hadamard. The 2x2 inverse and Pro FPGAs and to TSMC 0.35gm standard cells. The forward transforms are identical. multitransform and multiparallelism architecture mapped to FPGAs could process from 124 millions to 3.2 billions of The Hadamard transforms are used to explore a residual samples per second, depending on the parallelism level correlation between the results of the DCT transform when selected. The standard cells version could process from 218.7 color samples are processed or when luma samples predicted millions to 3.5 billions of samples per second. These results from intra 16xl6 mode are processed [3]. indicate that the proposed solution presents a high flexibility All H.264/AVC transforms use just integer arithmetic to and that this solution is able to be used in various H.264/AVC * a codecs with different performance requirements. The avoid the mismatch between forward and inverse transforms performance results of all experiments realized indicated that and to allow efficient hardware implementations [4]. this architecture is able to be used in high definition This work presents the architectural design of a applications, like HDTV. multitransform and multiparallelism IP that is able to calculate the five H.264/AVC transforms and that supports I. INTRODUCTION five different parallelism levels. Other characteristic of the proposed IP is that the number of input data bits is definedThe H.264/AVC (as know as MeG-4 lpart 10 h1e]e through an input parameter. This solution is highly flexible a video coding standard that has been developed to achieve and is able to be used in H.264/AVC codec designs with a significant improvements, i the compression performance, large spectrum of performance requirements.Over the existing standards. The second section of this paper presents some relatedThe main blocks of a H.264/AVC encoder are the motion wok.Tescintrepsnsth cre fte estimation, the motion compensation, the intra prediction, the multitransform and its characteristics. Section four presents loop filter the entropy coder, the forward and inverse the input and output parallelism controller. The fifth section quantization and the forward and inverse transforms. The presents the synthesis results for Altera and Xilinx FPGAs H.264/AVC decoder iS formed by entropy decoder, motion peet h ytei eut o leaadXln PA Hom264/aVCtdeodr isa formedicbyoentroopy decer, mion and for standard cell technologies. The conc...

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In the physical synthesis of integrated circuits the legalization step may move all circuit cells to fix overlaps and misalignments. While doing so, it should cause the smallest perturbation possible to the solution found by previous optimization steps to preserve placement quality. Legalization techniques must handle circuits with millions of cells within acceptable runtimes, besides facing other issues such as mixed-cell-height and fence regions. In this work we propose a k-d tree data structure to partition the circuit, thus removing data dependency. Then, legalization is sped up through both input size reduction and parallel execution. As a use case we employed a modified version of the classic legalization algorithm Abacus. Our solution achieved a maximum speedup of 35 times over a sequential version of Abacus for the circuits of the ICCAD2015 CAD contest. It also provided up to 10% reduction on the average cell displacement.

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