High Throughput FPGA Based Architecture for H. 264/AVC Inverse Transforms and Quantization

A framework for hardware reconfiguration using the digital TV signal

“…Another important issue that must be taken into consideration is that the industrial sector provides a collection of reference codes, such as circuits and modules in HDL, bit streams synthesized for different architectures and also HDLs for circuit simulation and validation [3] [6]. In the DTV area, the focus of this work, research projects seen in [4] and [5] show the use of FPGA for decoding H.264 video. The results are satisfactory and indicate that the use of these devices is possible for DTV receivers.…”

Design and FPGA prototyping of a H: 264/AVC main profile decoder for HDTV

“…The inverse transforms were designed to perform the two dimensional calculations without using the separability property. Then, the first step to design them was to decompose their mathematical definition [7] in algorithms that do not use the separability property [8]. The architectures designed for the inverse transforms use only one operator at each pipeline stage to save hardware resources.…”

“…The architectures designed for the inverse transforms use only one operator at each pipeline stage to save hardware resources. The architectures of the 2-D IDCT and of the 4x4 2-D inverse Hadamard were designed in a pipeline with 4 stages, with 64 cycles of latency [8]. The 2-D inverse Hadamard was designed in a pipeline with 2 stages, with 8 cycles of latency.…”

“…Some preliminary results of this architecture were presented in [1,8]. There are one luma and one chroma datapaths for motion compensation of the blocks.…”

FPGA Based Architectures for H. 264/AVC Video Compression Standard

“…The post place-and-route synthesis results indicate that this architecture is able to process 132 million of samples per second, allowing its use in H.264/AVC coders and decoders for HDTV. We do not find in the literature a solution that considers the complete operations of these blocks, but some comparisons were realized with partial solutions of these blocks and these comparisons are presented in [6]. The partial solutions focuses in very high throughputs and this implies in several difficulties to use these architectures inside of a complete solution for these blocks.…”