A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design

Monteiro, J.; Güntzel, José Luís; Agostini, Luciano

doi:10.1109/icecs.2011.6122308

Cited by 10 publications

(6 citation statements)

References 6 publications

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“…Such high performance devices need low power and area efficient adder circuits. The choice of adder architecture is of utmost importance, since its performance determines the whole system response [3]. For the implementation of fast adder, CLA principle is more optimized as it consumes less amount of time duration to calculate final carry bit.…”

Section: Introductionmentioning

confidence: 99%

Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

Kaswan

Munje

Kothari

et al. 2013

2013 International Conference on Advanced Electronic Systems (ICAES)

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The paper presents the implementation of a high speed energy efficient 4-bit binary CLA based incrementer decrementer. The design methodology is extensively based on static CMOS logic and transmission gate logic to achieve higher operating frequencies, smaller delays and optimized area. This circuit is especially suitable for long bit incrementer/decrementer that can be used in program counter, frequency dividers and address generation unit in microprocessors. Simulation results illustrates that the designed adder has superior performance compared to existing adders in terms of power dissipation and speed. The proposed circuit is implemented on TSMC 0.18um process model. The measurement results indicate that the proposed 4-bit incrementer/decrementer can operate up to 5GHz with 200x160 um 2 optimized area.

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Section: Introductionmentioning

confidence: 99%

Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

Kaswan

Munje

Kothari

et al. 2013

2013 International Conference on Advanced Electronic Systems (ICAES)

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“…Amelifard, Fallah, and Pedram (2005) proposed a CSA with a sharing scheme using latches which reduces area and power consumption but its delay performance is limited by RCA block at LSB stage, a close trade-off between performance, area and power is not maintained. Monteiro, Guntzel, and Agostini (2011) proposed two energy efficient Add-One Carry-Select Adders suitable for standard-cell synthesis (A1CSA and AICSAH). There are two approaches in A1CSA, with and without multiplexer.…”

Section: Introductionmentioning

confidence: 99%

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

Shanmugam

Choi

2014

International Journal of Electronics

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A Carry-Select Adder (CSA) is one of the most suitable adders for high-speed applications, but the power and area penalties are greater, because it requires a double Ripple-Carry Adder (RCA) structure corresponding to carry inputs 0 and 1. Current low-power and low-area techniques are not suitable for a standard cell-based design which is one of the widely adopted design methodologies. Our work proposes two simple optimised architectures suitable for standard cell-based designs. A simple decision logic that replaces the RCA for Carry input 1 in a conventional CSA is proposed. One of the proposed architectures reduces power and area significantly with a small delay penalty compared to the existing techniques. Another proposed architecture improves the speed of operation and reduces the power and area considerably. The first one is more suitable for high-speed arithmetic in battery-operated applications where there is a trade-off between speed and power, while the other one is suitable for high-performance applications which also require area and power optimisation. The proposed architectures were implemented in TSMC 0.18um CMOS technology, and compared with conventional Square Root Carry-Select Adders and an existing standard cell-based design.

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“…Thus, optimizing the adder circuitry to reduced power consumption will have a beneficial effect on many types of digital modules. Carry-Look ahead Adder (CLA) is fast adder architecture optimized at the logic-level, and used to design a high performance addition-based arithmetic circuits using cell based VLSI design [2]. Many design architecture and techniques have been developed to reduce power dissipation complementary logic.…”

Section: Introductionmentioning

confidence: 99%

Analysis & implementation of ultra low-power 4-bit CLA in subthreshold regime

Gupta

Munje

Kaswan

et al. 2014

2014 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014]

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The paper presents the analysis and implementation of ultra low-power, low voltage and low area 4-bit carry look ahead adder circuits. Sub-threshold design technique has been used to reduce the power consumption and area while maintaining low complexity of logic design in the proposed circuit. Simulation results illustrate the superiority of the circuits in sub-threshold region against the conventional low power design technique, in terms of power, area and power delay product (PDP). The CLA is implemented on TSMC 0.18μm process models in Cadence Virtuoso Schematic composer with improved driving ability and circuit robustness at 0.4V single ended supply voltage and simulations are carried out on Spectre S. The proposed 4-bit CLA can operate up to 5 MHz and used 0.035 µW of power and occupied an area of 60x92.5 µm 2 . Keywords-Carry look ahead adder (CLA); Power delay product (PDP) ; sub-threshold; Carry ripple adder(CRA)I.

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A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design

Cited by 10 publications

References 6 publications

Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

Analysis & implementation of ultra low-power 4-bit CLA in subthreshold regime

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A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design

Cited by 10 publications

References 6 publications

Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

Analysis &amp; implementation of ultra low-power 4-bit CLA in subthreshold regime

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Analysis & implementation of ultra low-power 4-bit CLA in subthreshold regime