Analysis & implementation of ultra low-power 4-bit CLA in subthreshold regime

Abstract

The paper presents the analysis and implementation of ultra low-power, low voltage and low area 4-bit carry look ahead adder circuits. Sub-threshold design technique has been used to reduce the power consumption and area while maintaining low complexity of logic design in the proposed circuit. Simulation results illustrate the superiority of the circuits in sub-threshold region against the conventional low power design technique, in terms of power, area and power delay product (PDP). The CLA is implemented on TSMC 0.18μm process models in Cadence Virtuoso Schematic composer with improved driving ability and circuit robustness at 0.4V single ended supply voltage and simulations are carried out on Spectre S. The proposed 4-bit CLA can operate up to 5 MHz and used 0.035 µW of power and occupied an area of 60x92.5 µm 2 . Keywords-Carry look ahead adder (CLA); Power delay product (PDP) ; sub-threshold; Carry ripple adder(CRA)I.

A Subthreshold Bootstrapped SAPTL-Based Adder Design

“…Pass transistors and transmission gates are usually used in this method for a smaller area and lower power, which has a finite effect on improving the performance. In addition, using fast adder architecture optimized at the logic level is also a viable method to enhance the circuit speed [18,19], such as carry look-ahead adder (CLA) design [15,18,20]. But these works mainly focus on the structure design of gate-level circuits, like an XOR gate, which still have difficulty in achieving an acceptable level of performance in the subthreshold region.…”