The paper presents the implementation of a high speed energy efficient 4-bit binary CLA based incrementer decrementer. The design methodology is extensively based on static CMOS logic and transmission gate logic to achieve higher operating frequencies, smaller delays and optimized area. This circuit is especially suitable for long bit incrementer/decrementer that can be used in program counter, frequency dividers and address generation unit in microprocessors. Simulation results illustrates that the designed adder has superior performance compared to existing adders in terms of power dissipation and speed. The proposed circuit is implemented on TSMC 0.18um process model. The measurement results indicate that the proposed 4-bit incrementer/decrementer can operate up to 5GHz with 200x160 um 2 optimized area.
The paper presents the analysis and implementation of ultra low-power, low voltage and low area 4-bit carry look ahead adder circuits. Sub-threshold design technique has been used to reduce the power consumption and area while maintaining low complexity of logic design in the proposed circuit. Simulation results illustrate the superiority of the circuits in sub-threshold region against the conventional low power design technique, in terms of power, area and power delay product (PDP). The CLA is implemented on TSMC 0.18μm process models in Cadence Virtuoso Schematic composer with improved driving ability and circuit robustness at 0.4V single ended supply voltage and simulations are carried out on Spectre S. The proposed 4-bit CLA can operate up to 5 MHz and used 0.035 µW of power and occupied an area of 60x92.5 µm 2 .
Keywords-Carry look ahead adder (CLA); Power delay product (PDP) ; sub-threshold; Carry ripple adder(CRA)I.
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