Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

Kaswan, Nikhil; Munje, Ishan; Kothari, Yash Chandresh; Gupta, Priya; Gupta, Anu

doi:10.1109/icaes.2013.6659370

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…For the combination of input X i and Y i adder stage I is said to propagate carries if it produces a carry out of 1 in presence of the input combination of X 0 -X i-1 , Y 0 -Y i-1 and C 0 that cause a carry in of 1 [3][4][5].Corresponding to this definition the logic equations for a carry generate signal G i and a carry propagate signal P i for each stage of carry look ahead adder. These above equations (3.1 -3.4) by using transmission gate logic will minimize number of transistors, Minimize all internal capacitances, by minimizing the active area of the transistors, and thus minimizing power [3,[6][7]. The P i and G i generator is designed by using the transmission gate base AND gate logic and XOR gate logic.…”

Section: Carry Look Ahead Addermentioning

confidence: 99%

A high speed low power adder in dynamic logic base on transmission gate

Jain¹,

Gour²,

Shrman³

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

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Speed of operation depends on the longest critical paths in the multi-bit adders and also the MOSFET transistor gain which in turn depends on transistor size. The power consumption in MOSFET is depends on the switching frequency, sub threshold leakage and switching time. In this paper, author proposed the speed and area efficient transistor base adder using static CMOS pass transistor logic, and shortened the longest critical path to decrease the total critical path delay. The design simulation on microwind layout tool calculates the worst-case delay in nanosecond and total power consumption in microwatt range.

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Section: Carry Look Ahead Addermentioning

confidence: 99%

A high speed low power adder in dynamic logic base on transmission gate

Jain¹,

Gour²,

Shrman³

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

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“…They design the multiplexer base full adder logic for their propose circuit [1]. The power consumption is optimize with minimum size for both NMOS and PMOS.…”

Section: Related Workmentioning

confidence: 99%

“…The power consumption is optimize with minimum size for both NMOS and PMOS. The W/L's of all transistors in the subsystems were kept in the ratio of 2:1 for the pull up and pull down network respectively [1]. The design the compuatational unit base on arithamatic adder which are identical for all adder units, so called Metamorphosis of Partial Full Adder (MPFA) and look ahead circuit.…”

Section: Related Workmentioning

confidence: 99%

Programmable High Speed 8-Bit Binary Incrementer Decrementer

Singh¹,

Tiwari²,

Khan³

2015

IJETT

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Abstract:This paper presents the eight bit CMOS base incrementer and decrementer logic design using eight bit adder and subtractor. The parametric simulation is done on MICROWIND layout editor tool. The any conventional static CMOS adder with pullup and pulldown logic requires 32 MOSFET whereas our design adder requires 30 MOSFETs. Our design methodology is based on static CMOS logic and transmission gate logic to achieve smaller delays, reduce power dissipation and optimized area. We can use a high-speed parallel adder in incrementer / decrementer to improve the operating speed which can count up or count down from the loaded value by one step in one clock cycle.

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Transmission Gate base Programmable Binary Incrementer Decrementer

Singh¹,

Tiwari²,

Khan³

2015

IJCA

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We can use a high-speed parallel adder in incrementer / decrementer to improve the operating speed which can count up or count down from the loaded value by one step in one clock cycle. For this, design of a faster and highly reliable adder is of major importance. Thus, much effort has been invested in the research that has led to faster and more efficient ways to perform this operation. To prove the efficiency of the proposed method, the circuit is simulated in pass transistor CMOS 50nm technology and some simulation parameters are calcultes in the layout of the circuit. The binary decrementer reduces the stored binary data in memopry or register by '1'. This can be done by using 2's complement method by using XOR gates which convert binary data in 1's complement and then by addition of binary '1' it can be converted to 2's complement form. It is made by cascading 'n' full adders for 'n' number of bits i.e. the storage capacity of the register to be decremented. Hence, a 4-bit binary decrementer requires 4 cascaded half adder circuits. This paper presents the eight bit CMOS base incrementer and decrementer logic design using eight bit adder and subtractor. The parametric simulation is done on MICROWIND layout editor tool. The any conventional static CMOS adder with pullup and pulldown logic requires 32 MOSFET whereas our design adder requires 30 MOSFETs. Our design methodology is based on static CMOS logic and transmission gate logic to achieve smaller delays, reduce power dissipation and optimized area.

show abstract

Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

Cited by 3 publications

References 6 publications

A high speed low power adder in dynamic logic base on transmission gate

A high speed low power adder in dynamic logic base on transmission gate

Programmable High Speed 8-Bit Binary Incrementer Decrementer

Transmission Gate base Programmable Binary Incrementer Decrementer

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