Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing

Livramento, Vinicius; Guth, Chrystian; Güntzel, José Luís; Johann, Marcelo

doi:10.7873/date.2013.370

Cited by 10 publications

(13 citation statements)

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“…In [6], foundations for LR-based gate sizing approach is first established, which considers continuous sizing and simple delay models. The LRbased approach is then continuously got improved as people are combining it with library-based timing model, discrete gate sizing, V th assignment, dynamic programming and network flow algorithms [18] [19] [20] [21]. The advantage of LRbased approach is that it can be easily modified to handle different objectives and various complex design constraints.…”

Section: A Gate Selection Techniques For Synchronous Circuitsmentioning

confidence: 99%

“…There are even organized gate sizing contests [16] [17] to help expose the challenges faced in modern industrial designs to the academic field. One powerful heuristic approach adopted by leading synchronous gate selection algorithms [18] [19] is to apply the Lagrangian relaxation (LR) technique. In [6], foundations for LR-based gate sizing approach is first established, which considers continuous sizing and simple delay models.…”

Section: A Gate Selection Techniques For Synchronous Circuitsmentioning

confidence: 99%

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Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation

Sharma

Chu

2015

2015 21st IEEE International Symposium on Asynchronous Circuits and Systems

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Gate sizing and threshold voltage selection is an important step in the VLSI physical design process to help reduce power consumption and improve circuit performance. Recent asynchronous design flows try to directly leverage synchronous EDA tools to select gates, which have a lot of limitations due to the intrinsic difference between asynchronous and synchronous circuits. This paper presents a new simultaneous gate sizing and Vth assignment approach for asynchronous designs. We formulate the asynchronous gate version selection problem considering both leakage power consumption and cycle time. Then, the optimization is performed based on a Lagrangian relaxation framework. A fast and effective slew updating strategy is also proposed to address the timing-loops of asynchronous circuits during static timing analysis. Our approach is evaluated using a set of asynchronous designs based on the pre-charged half buffer (PCHB) template and compared with the Proteus asynchronous design flow which is leveraging synchronous EDA tools. The experiments show our approach can achieve much better quality results in terms of both leakage power and cycle time compared with the other approach.

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Section: A Gate Selection Techniques For Synchronous Circuitsmentioning

confidence: 99%

Section: A Gate Selection Techniques For Synchronous Circuitsmentioning

confidence: 99%

Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation

Sharma

Chu

2015

2015 21st IEEE International Symposium on Asynchronous Circuits and Systems

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“…The performance of Lagrangian relaxation techniques on ISPD-2012 benchmarks was described in [11,12]. Empirically, runtimes show significant improvement over [7], but at the cost of increased leakage.…”

Section: Comparisons To Prior Researchmentioning

confidence: 99%

“…Empirically, runtimes show significant improvement over [7], but at the cost of increased leakage. Interconnect delay modeling and optimization are not discussed in [11,12]. These considerations completely change the nature of the overall optimization, making it impossible to reliably extrapolate the performance of Lagrangian relaxation to the ISPD-2013 benchmark suite, as several algorithmic components must be developed to enable a full comparison.…”

Section: Comparisons To Prior Researchmentioning

confidence: 99%

High-performance gate sizing with a signoff timer

Kahng

Kang

Lee

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Process and device scaling in late-CMOS technologies highlight leakage power as a critical challenge for the semiconductor industry. Careful gate sizing and V th -swapping can reduce leakage, but prior optimizations based on convex or dynamic programming (i) are often based on unrealistic assumptions about circuit delay and slew propagation, (ii) fail to handle practical design rules such as transition time or load upper bounds, and (iii) do not scale well to input complexities when full extracted parasitics are available. Seeing substantial opportunities for improvement, we present a multithreaded, stochastic optimization (Trident2.0) for gate sizing and V th assignment to minimize leakage power subject to capacitance, slew and timing constraints. Scalability and high performance of Trident2.0 are validated on ISPD-2013 Gate Sizing Contest benchmarks.

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“…For a fair assessment, we obtain timing-feasible solutions for all testcases. Our approach uses the academic tool [17] to perform timing recovery and changes .sdc files to generate timing-feasible solutions. Issue C2: For assessment across different technologies, we would like to ensure that input netlists and sizing/Vt solution spaces are preserved across technologies.…”

Section: Enablement Of Gate Sizing Assessmentsmentioning

confidence: 99%

Horizontal benchmark extension for improved assessment of physical CAD research

Kahng

Lee

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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The rapid growth in complexity and diversity of IC designs, design flows and methodologies has resulted in a benchmark-centric culture for evaluation of performance and scalability in physicaldesign algorithm research. Landmark papers in the literature present vertical benchmarks that can be used across multiple design flow stages; artificial benchmarks with characteristics that mimic those of real designs; artificial benchmarks with known optimal solutions; as well as benchmark suites created by major companies from internal designs and/or open-source RTL. However, to our knowledge, there has been no work on horizontal benchmark creation, i.e., the creation of benchmarks that enable maximal, comprehensive assessments across commercial and academic tools at one or more specific design stages. Typically, the creation of horizontal benchmarks is limited by mismatches in data models, netlist formats, technology files, library granularity, etc. across different tools, technologies, and benchmark suites. In this paper, we describe methodology and robust infrastructure for "horizontal benchmark extension" that permits maximal leverage of benchmark suites and technologies in "apples-to-apples" assessment of both industry and academic optimizers. We demonstrate horizontal benchmark extensions, and the assessments that are thus enabled, in two well-studied domains: place-and-route (four combinations of academic placers/routers, and two commercial P&R tools) and gate sizing (two academic sizers, and three commercial tools). We also point out several issues and precepts for horizontal benchmark enablement.

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Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing

Cited by 10 publications

References 0 publications

Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation

Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation

High-performance gate sizing with a signoff timer

Horizontal benchmark extension for improved assessment of physical CAD research

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