Horizontal benchmark extension for improved assessment of physical CAD research

Kahng, Andrew B.; Lee, Hyein; Li, Jiajia

doi:10.1145/2591513.2591540

Cited by 21 publications

(5 citation statements)

References 33 publications

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“…Benchmarks: We conduct our comprehensive experiments using in total 28 benchmarks, selected not only from the "traditional" suites (i.e., ISCAS-85, MCNC, and ITC-99), but also from the large-scale IBM superblue suite [22]. For the latter, we leverage scripts from [23] to generate LEF/DEF files, but we also use the Nangate 45nm library [21] while doing so.…”

Section: Experimental Investigationmentioning

confidence: 99%

See 1 more Smart Citation

Concerted wire lifting: Enabling secure and cost-effective split manufacturing

Patnaik¹,

Knechtel²,

Ashraf³

et al. 2018

2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)

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Here we advance the protection of split manufacturing (SM)-based layouts through the judicious and well-controlled handling of interconnects. Initially, we explore the cost-security trade-offs of SM, which are limiting its adoption. Aiming to resolve this issue, we propose effective and efficient strategies to lift nets to the BEOL. Towards this end, we design custom "elevating cells" which we also provide to the community. Further, we define and promote a new metric, Percentage of Netlist Recovery (PNR), which can quantify the resilience against gate-level theft of intellectual property (IP) in a manner more meaningful than established metrics. Our extensive experiments show that we outperform the recent protection schemes regarding security. For example, we reduce the correct connection rate to 0% for commonly considered benchmarks, which is a first in the literature. Besides, we induce reasonably low and controllable overheads on power, performance, and area (PPA). At the same time, we also help to lower the commercial cost incurred by SM. 1 We advocate the terminology "to split after" instead of the commonly used "to split at." For example, "to split at M2" remains ambiguous whether M2 is still within the FEOL or already in the BEOL. Further, the same uncertainty applies to the vias of V12 and V23, i.e., those between M1/M2 and M2/M3, respectively. Our definition for "to split after M2" is that M2 and V12 are still in the FEOL, while the vias of V23 are already in the BEOL.

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Section: Experimental Investigationmentioning

confidence: 99%

“…Placement Perturbation [12] Routing Perturbation [15] Proposed [12] tends to provide netlists with combinatorial loops, hindering their simulation. Those netlists have been post-processed using scripts of [23]. For the benchmark c6288, the post-processed netlist still fails simulation, due to "UNKNOWN" nets.…”

Section: Benchmark Original Layoutmentioning

confidence: 99%

Concerted wire lifting: Enabling secure and cost-effective split manufacturing

Patnaik¹,

Knechtel²,

Ashraf³

et al. 2018

2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…Test cases: We evaluate our proposed defense on 12 benchmarks, seven from the ISCAS-85 suite and five from the industrial IBM superblue suite [14]. We convert the superblue benchmarks (initially defined in Bookshelf format) to Verilog files using scripts from [15].…”

Section: Methodsmentioning

confidence: 99%

Raise your game for split manufacturing

Patnaik¹,

Ashraf²,

Knechtel³

et al. 2018

Proceedings of the 55th Annual Design Automation Conference

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Split manufacturing (SM) seeks to protect against piracy of intellectual property (IP) in chip designs. Here we propose a scheme to manipulate both placement and routing in an intertwined manner, thereby increasing the resilience of SM layouts. Key stages of our scheme are to (partially) randomize a design, place and route the erroneous netlist, and restore the original design by re-routing the BEOL. Based on state-of-the-art proximity attacks, we demonstrate that our scheme notably excels over the prior art (i.e., 0% correct connection rates). Our scheme induces controllable PPA overheads and lowers commercial cost (the latter by splitting at higher layers).Wang et al. [5] proposed an advanced proximity attack which utilizes multiple hints from the FEOL layouts: (i) physical proximity of gates, (ii) avoidance of combinatorial loops, (iii) constraints on load capacitances, (iv) direction of "dangling wires" 1 , and (v) timing constraints. Magaña et al. [6,7] proposed different attack schemes, whereupon they empirically observe that attacks considering routing paths/utilization are more effective than placement-centric attacks. They also observe that the IBM superblue suite is considerably more challenging to attack than "traditional," small-scale benchmarks. Note that their attacks do not recover actual netlists, but only list possible candidates for each net to reconnect.Key attack metrics, as discussed in [3,5,12], are the Hamming distance (HD), the correct connection rate (CCR), and the output error rate (OER). The HD quantifies the mismatch between the outputs of an original and the outputs of a recovered/stolen netlist during test stimulation. An HD of 0% (or 100%) denotes attack success. The 1 There are metal segments left open/unconnected in the topmost FEOL layer, namely where the vias connecting upward to the BEOL are to be placed. These metal segments are referred to as "dangling wires. " Moreover, we refer to the locations for those vias connecting with the BEOL as virtual pins (vpins), as in [6,7].

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“…Benchmarks: We conduct our experiments on traditional benchmarks suites (ISCAS-85, MCNC, and ITC-99), on the large-scale EPFL suite [33], and on the industrial IBM superblue circuits [34] (Table III). For the IBM superblue circuits, we leverage [38] to synthesize and generate the layouts for further analysis. As for SAT attacks, we pre-process the sequential circuits (IBM superblue) as follows: the inputs (and outputs) of all flip-flops become primary outputs (and inputs); thereafter, the flip-flops are removed.…”

Section: Security Analysis a Study On Large-scale Ip Protection Amentioning

confidence: 99%

Advancing hardware security using polymorphic and stochastic spin-hall effect devices

Patnaik

Rangarajan

Knechtel

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Protecting intellectual property (IP) in electronic circuits has become a serious challenge in recent years. Logic locking/encryption and layout camouflaging are two prominent techniques for IP protection. Most existing approaches, however, particularly those focused on CMOS integration, incur excessive design overheads resulting from their need for additional circuit structures or device-level modifications. This work leverages the innate polymorphism of an emerging spin-based device, called the giant spin-Hall effect (GSHE) switch, to simultaneously enable locking and camouflaging within a single instance. Using the GSHE switch, we propose a powerful primitive that enables cloaking all the 16 Boolean functions possible for two inputs. We conduct a comprehensive study using state-of-the-art Boolean satisfiability (SAT) attacks to demonstrate the superior resilience of the proposed primitive in comparison to several others in the literature. While we tailor the primitive for deterministic computation, it can readily support stochastic computation; we argue that stochastic behavior can break most, if not all, existing SAT attacks. Finally, we discuss the resilience of the primitive against various side-channel attacks as well as invasive monitoring at runtime, which are arguably even more concerning threats than SAT attacks.

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Horizontal benchmark extension for improved assessment of physical CAD research

Cited by 21 publications

References 33 publications

Concerted wire lifting: Enabling secure and cost-effective split manufacturing

Concerted wire lifting: Enabling secure and cost-effective split manufacturing

Raise your game for split manufacturing

Advancing hardware security using polymorphic and stochastic spin-hall effect devices

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