Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation

Abstract

Gate sizing and threshold voltage selection is an important step in the VLSI physical design process to help reduce power consumption and improve circuit performance. Recent asynchronous design flows try to directly leverage synchronous EDA tools to select gates, which have a lot of limitations due to the intrinsic difference between asynchronous and synchronous circuits. This paper presents a new simultaneous gate sizing and Vth assignment approach for asynchronous designs. We formulate the asynchronous gate version selection problem considering both leakage power consumption and cycle time. Then, the optimization is performed based on a Lagrangian relaxation framework. A fast and effective slew updating strategy is also proposed to address the timing-loops of asynchronous circuits during static timing analysis. Our approach is evaluated using a set of asynchronous designs based on the pre-charged half buffer (PCHB) template and compared with the Proteus asynchronous design flow which is leveraging synchronous EDA tools. The experiments show our approach can achieve much better quality results in terms of both leakage power and cycle time compared with the other approach.

Physical design algorithms for asynchronous circuits

“…• A gate sizing and V th assignment approach for asynchronous circuits [89]. We also proposed a fast and effective slew updating strategy which is able to address the timing-loops of asynchronous circuits during static timing analysis.…”

“…For an asynchronous circuit modeled with FBCN, our primal problem which minimizes total leakage power subject to performance constraints can be formulated similar to [89] as shown below:…”

“…However, those works cannot be directly applied to asynchronous circuits, due to the intrinsic differences between asynchronous and synchronous circuits in terms of performance analysis and optimization. In [89], a gate sizing and V th assignment approach for asynchronous circuits has been proposed. It achieved significant improvements compared with previous asynchronous gate sizing approaches.…”

“…Then, evaluation is performed for this modified circuit before the next move [63] [86]. Similarly, in the gate sizing process of circuits, the algorithm might adjust the size of one gate at a time, instead of changing the sizes of all the gates at once [89]. Considering the above type of applications which only few changes are made at each step, the MCR algorithm might also be able to do the calculation "incrementally" by leveraging the information calculated at the previous step, and therefore be able to find the MCR much faster.…”