High Throughput Multitransform and Multiparallelism IP for H.264/AVC Video Compression Standard

Abstract

This paper presents the design of a high The forward transform block uses three different throughput multitransform and multiparallelism IP for transforms, depending on the type of input data. This H.264/AVC standard. This solution supports the five transforms are 4x4 FDCT, 4x4 forward Hadamard and 2x2 H.264/AVC transforms and it supports five different levels of forward Hadamard. The inverse transform block is also parallelism. The proposed architecture were described in formed by three different transforms: 4x4 IDCT, 4x4 inverse VHDL and synthesized to Altera Stratix and Xilinx Virtex-It Hadamard and 2x2 inverse Hadamard. The 2x2 inverse and Pro FPGAs and to TSMC 0.35gm standard cells. The forward transforms are identical. multitransform and multiparallelism architecture mapped to FPGAs could process from 124 millions to 3.2 billions of The Hadamard transforms are used to explore a residual samples per second, depending on the parallelism level correlation between the results of the DCT transform when selected. The standard cells version could process from 218.7 color samples are processed or when luma samples predicted millions to 3.5 billions of samples per second. These results from intra 16xl6 mode are processed [3]. indicate that the proposed solution presents a high flexibility All H.264/AVC transforms use just integer arithmetic to and that this solution is able to be used in various H.264/AVC * a codecs with different performance requirements. The avoid the mismatch between forward and inverse transforms performance results of all experiments realized indicated that and to allow efficient hardware implementations [4]. this architecture is able to be used in high definition This work presents the architectural design of a applications, like HDTV. multitransform and multiparallelism IP that is able to calculate the five H.264/AVC transforms and that supports I. INTRODUCTION five different parallelism levels. Other characteristic of the proposed IP is that the number of input data bits is definedThe H.264/AVC (as know as MeG-4 lpart 10 h1e]e through an input parameter. This solution is highly flexible a video coding standard that has been developed to achieve and is able to be used in H.264/AVC codec designs with a significant improvements, i the compression performance, large spectrum of performance requirements.Over the existing standards. The second section of this paper presents some relatedThe main blocks of a H.264/AVC encoder are the motion wok.Tescintrepsnsth cre fte estimation, the motion compensation, the intra prediction, the multitransform and its characteristics. Section four presents loop filter the entropy coder, the forward and inverse the input and output parallelism controller. The fifth section quantization and the forward and inverse transforms. The presents the synthesis results for Altera and Xilinx FPGAs H.264/AVC decoder iS formed by entropy decoder, motion peet h ytei eut o leaadXln PA Hom264/aVCtdeodr isa formedicbyoentroopy decer, mion and for standard cell technologies. The conc...

Efficient inverse transform architectures for multi-standard video coding applications

“…The matrix product operations of the 1-D VC-1 8-point inverse transform in (11) can be divided into eight submatrices, denoted as …”

“…The 4-point transforms can be realised using 1-D transform units and one 4 × 4 transpose memory unit [6][7][8]. The 4 × 4 transpose memory unit can be reduced by using 2-D transform approaches to increase throughput to up to 8 or 16 pixels/cycle [9][10][11][12]. The 2-D transform procedure was constructed using eight 1-D transform units without the 4 × 4 transpose memory unit in [13], achieving a throughput of 16 pixels/cycle.…”

“…Since the matrices in (1), (4), (8),(11) and(16) are distinct, the straightforward method realises the transform architectures individually. In the proposed unified architecture, the 8-, 4-and 2-point inverse transforms for the three standards are combined using a single-transform procedure.…”

Design and FPGA prototyping of a H: 264/AVC main profile decoder for HDTV

“…The solutions proposed in [9,10,11,12] are multitransform architectures that are able to process the calculations related to the four 4x4 forward and inverse transforms. Our design solution [9] processes also the 2x2 forward and inverse Hadamards and this solution is able to select the level of parallelism desired in the computations. The designs presented in [13] grouped individually each 4x4 transform with their specific quantization, but they do not group a complete inverse transforms and quantization module.…”

FPGA Based Architectures for H. 264/AVC Video Compression Standard

“…This IP uses an input and an output controller to allow de multiparallelism operation. The synthesis results of this architecture were presented in [8] and reaches very high throughputs. These results, according with the selected parallelism level, allow a processing rate varying from 123 millions of samples per second to 3.5 billions of samples per second, allowing its use in H.264/AVC codecs for HDTV.…”