Efficient inverse transform architectures for multi-standard video coding applications

Abstract

Hardware designs that can support multiple standards are required for versatile media players. The study proposes a unified inverse transform architecture that can be efficiently used in Moving Picture Expert Group and ITU International Telecommunication Standardisation Sector (ITU-T) H.264/advanced video coding (AVC), Microsoft video codec 1 (VC-1) and Chinese Audio Video Coding Standard (AVS) decoders. For H.264/AVC 8-, 4-and 2-point inverse transforms, the computational complexity in the proposed architecture is similar to that defined in the H.264/AVC standard. By using the symmetry of the transform matrices, the matrix product operations of the inverse transforms in VC-1 and AVS are efficiently decomposed to use only shifters, adders and subtractors. All the computations are verified and designed using a hardware unit to achieve a low-cost hardware kernel. The proposed multiple-transform architecture contains fast 1-D transforms and rounding operations for the computation of H.264/AVC, VC-1 and AVS 8-and 4-point inverse transforms. Simulation results show that the total number of gates for the proposed architecture is 8983, which is much lower than that required for architectures without hardware sharing. Compared with individual designs, the proposed shared architecture reduces the number of logic gates by a factor of two with a penalty of 20% in data throughput.