Energy-Efficient Hadamard-Based SATD Architectures

Cancellier, Luiz Henrique; Bräscher, André Beims; Seidel, Ismael; Güntzel, José Luís

doi:10.1145/2660540.2661004

Cited by 11 publications

(5 citation statements)

References 20 publications

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“…However, the second WHT stage uses the output of the first stage, so a buffer is needed between them if the transforms are not fully parallel. Several architecture explorations between parallel and buffer-based schemes can be found in the literature [15], [16], [21], [22]. A two-stage architecture with a TB [12] between the stages has proven to be a good tradeoff between energy consumption and area, so it was selected as basis for this work.…”

Section: Proposed Hardware Satd Implementationmentioning

confidence: 99%

“…In TE-SATD, the second 1-D stage exploits specific properties of absolute values to reduce arithmetic operations. The works in [21], [22] compared different 4×4 TE-SATD and butterfly-based FWHT-SATD architectures, of which TE-SATD architectures turned out to be more area and energy efficient. In [23], the authors introduced a combined 4×4 and 8×8 SATD hardware architecture, which deployed also TE-SATD.…”

Section: Introductionmentioning

confidence: 99%

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High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

Partanen

Lemmetti

Sjövall

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents the first known high-level synthesis (HLS) implementation for the Sum of Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture is designed for two SATD algorithms: a widespread Fast Walsh-Hadamard Transform (FWHT-SATD) and a recently introduced Transform Exempted scheme (TE-SATD). This 2-stage architecture is made up of two 1-D Walsh-Hadamard Transform (WHT) stages and a transpose buffer (TB) between them. The chosen HLS approach cuts down design time over contemporary design methods and thereby made it feasible to implement a set of dedicated FWHT-SATD and TE-SATD architectures for 4×4, 8×8, and 16×16 pixel blocks. All these six architectures were synthesized for 28 nm and 45 nm standard cell technologies, and their area and energy consumptions were analysed. TE-based implementations provide 6.0-8.3% total cell area savings and 6.9-12.7% better energy-efficiency than traditional FWHT approaches. Our proposal is the first to introduce TE-SATD architectures for up to 16×16 blocks and each of these tailored architectures was shown to provide better trade-off between silicon area and performance than their reference implementations.

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Section: Proposed Hardware Satd Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

Partanen

Lemmetti

Sjövall

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Soares et al [15] and Cancellier et al [16] both implement SATD architectures. However, even though the architectures implement absolute operators, no details are given on how they are implemented.…”

Section: Related Workmentioning

confidence: 99%

Exploring Absolute Differences Arithmetic Operators for Power and Area-Efficient SAD Hardware Architectures

Abreu

Grellert

Paim

et al. 2020

JICS

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Managing the energy requirements of video encoders has been an important research topic throughout the latest years, given the limited resources of battery-powered systems. Sum of Absolute Differences (SAD) stands out among the most costly steps in the video encoding process compliant with the High Efficiency Video Coding (HEVC) standard. This metric is mainly used to explore temporal redundancies during the inter prediction stage of the encoder, and it is applied by adding the absolute differences of the colocalized pixels of two video blocks, as a means of measuring the similarity between them. SAD architectures are usually designed by using an adder tree, with its first level consisting of subtractors and absolute operators. This paper explores various structures of absolute operators in the context of SAD architectures, in order to define the most suitable implementation for a power-efficient SAD module. Besides the analysis of several different models, we exploit the use of pipelining, and the impact of varying block input bitwidth, to determine which versions scale better with the increase of input size. We have synthesized the architectures for ASIC CMOS technology using real-input vectors taking the delays into consideration, with an ST 65 nm standard cells library, and compared them with the default absolute operator macrofunction from the synthesis tool.

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“…To the best of our knowledge, none of the publications on the TE-SATD method present hardware architectures, while [10] simply evaluated the number of saved operations in relation to the MMB and FHT methods. In our previous work [18] we analyzed the area and energy of some Hadamard-based SATD architectures.…”

Section: Introductionmentioning

confidence: 99%

Exploring Optimized Hadamard Methods to Design Energy-Efficient SATD Architectures

Cancellier¹,

Seidel²,

Bräscher³

et al. 2020

JICS

Self Cite

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State-of-the-art video coding tools are submitted to severe performance and energy consumption requirements resulting from high complexity of video standards and from limited energy budgets of portable mobile devices. While providing most of the compression gains, inter frame and intra frame prediction techniques are the most demanding steps, since they compare a huge number of blocks. In such a process, the similarity metric employed affects both the quality of compression and the calculation effort. In this paper we propose the use of Hadamardbased Sum of Absolute Transformed Differences (SATD), in replacement of the traditionally used Sum of Absolute Differences (SAD), as a means of improving the efficiency of video coding. To allow that we explore two Hadamard Transform methods to design efficient SATD architectures, one using the Fast Hadamard Transform (FHT) butterfly and another one using the so-called Transform-Exempted (TE) SATD algorithm. Those methods were combined with architectural decisions (full parallelism, full parallelism with pipelining or multi-cycling) to build a total of six Hadamard-based SATD architectures that were synthesized for a commercial 45nm standard cell library for two operating frequencies. The architectures were simulated with pixel block data to obtain realistic dynamic power and energy estimates. The TE-SATD architectures achieved the lowest energy results: down to 13.13 pJ/SATD in the case of parallel architecture with pipeline. However, considering also the area results when evaluating energy, the best results are given by both methods using multi-cycling (transpose buffer): nearly 20.75 pJ/SATD with up to 63.54% smaller area compared with fully parallel architectures.

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Energy-Efficient Hadamard-Based SATD Architectures

Cited by 11 publications

References 20 publications

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

Exploring Absolute Differences Arithmetic Operators for Power and Area-Efficient SAD Hardware Architectures

Exploring Optimized Hadamard Methods to Design Energy-Efficient SATD Architectures

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