Exploring Optimized Hadamard Methods to Design Energy-Efficient SATD Architectures

Abstract

State-of-the-art video coding tools are submitted to severe performance and energy consumption requirements resulting from high complexity of video standards and from limited energy budgets of portable mobile devices. While providing most of the compression gains, inter frame and intra frame prediction techniques are the most demanding steps, since they compare a huge number of blocks. In such a process, the similarity metric employed affects both the quality of compression and the calculation effort. In this paper we propose the use of Hadamardbased Sum of Absolute Transformed Differences (SATD), in replacement of the traditionally used Sum of Absolute Differences (SAD), as a means of improving the efficiency of video coding. To allow that we explore two Hadamard Transform methods to design efficient SATD architectures, one using the Fast Hadamard Transform (FHT) butterfly and another one using the so-called Transform-Exempted (TE) SATD algorithm. Those methods were combined with architectural decisions (full parallelism, full parallelism with pipelining or multi-cycling) to build a total of six Hadamard-based SATD architectures that were synthesized for a commercial 45nm standard cell library for two operating frequencies. The architectures were simulated with pixel block data to obtain realistic dynamic power and energy estimates. The TE-SATD architectures achieved the lowest energy results: down to 13.13 pJ/SATD in the case of parallel architecture with pipeline. However, considering also the area results when evaluating energy, the best results are given by both methods using multi-cycling (transpose buffer): nearly 20.75 pJ/SATD with up to 63.54% smaller area compared with fully parallel architectures.

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

“…Table III presents these results for the proposed and related TBbased SATD architectures. In comparison with the existing 4×4 SATD architectures [15], [22], the proposed solution has competitive area, although it only takes one-fifth and onefourth of their clock periods, respectively. In the case of 8×8 SATD architectures, the proposed work is the smallest.…”

“…However, the second WHT stage uses the output of the first stage, so a buffer is needed between them if the transforms are not fully parallel. Several architecture explorations between parallel and buffer-based schemes can be found in the literature [15], [16], [21], [22]. A two-stage architecture with a TB [12] between the stages has proven to be a good tradeoff between energy consumption and area, so it was selected as basis for this work.…”

“…In TE-SATD, the second 1-D stage exploits specific properties of absolute values to reduce arithmetic operations. The works in [21], [22] compared different 4×4 TE-SATD and butterfly-based FWHT-SATD architectures, of which TE-SATD architectures turned out to be more area and energy efficient. In [23], the authors introduced a combined 4×4 and 8×8 SATD hardware architecture, which deployed also TE-SATD.…”

Variable Block Size Fractional Motion Estimation Hardware Architecture for VVC and HEVC Standards

“…Other distortion metrics may be used to improve coding efficiency, such as the Hadamard-based Sum of Absolute Transformed Differences (SATD) [24,25], but with a considerable price in terms of executed operations.…”