In this work 3D-TCAD simulation is used to investigate and harden single event latch-up (SEL) occurring in embedded SRAMs, in both 130 nm and 65 nm Flash-based Field Programmable Gate Arrays (FPGAs). The methodology to perform accurate SEL simulations on realistic designs suitable for high volume manufacturing is presented. One important new finding is that depending on the technology node, the number of SRAM cells included in the 3D structure significantly affects the SEL threshold. The number of SRAM cells needs to be optimized for accurate SEL prediction within a reasonable simulation time.The simulation results are validated using heavy ion and neutron data. After trade-off studies, process mitigation solutions are chosen to improve the SEL threshold in 65 nm and achieve immunity in neutron environment.Index Terms-3D-TCAD simulation, flash-based FPGA, single event latch-up, SRAMs.

In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz.

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