Neutron SEE Testing of the 65nm SmartFusion2 Flash-Based FPGA

Dsilva, Durwyn; Wang, Jih-Jong; Rezzak, Nadia; Jat, Narayan

doi:10.1109/redw.2015.7336722

Cited by 13 publications

(7 citation statements)

References 1 publication

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“…These setups offer a compact and effective testing platform for HARV-SoC. In particular, regarding the configuration memory, the flash-based FPGA provides high immunity to SEEs [27], improving the platform's availability for the experiment. Also, the usage of a custom transceiver solution mitigated logging errors that could affect post-irradiation analysis, since they are based on a robust industrial protocol that reduces the amount of complex and sensitive components in the irradiation room (e.g., serial to USB converters, USB extenders).…”

Section: Methodsmentioning

confidence: 99%

Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip

et al. 2023

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Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables the implementation and customization of the processor features to increase their reliability. Studies on hardened RISC-V processors facing harsh radiation environments apply fault tolerance techniques in the processor core and peripherals, exploiting system redundancies. In prior work, we present a hardened RISC-V System-on-Chip (SoC), which could detect and correct radiation-induced faults with limited fault awareness. Therefore, in this work, we propose solutions to extend the fault observability of the SoC implementation by providing error detection and monitoring. For this purpose, we introduce observation features in the redundant structures of the system, enabling the report of valuable information that supports enhanced radiation testing and support the application to perform actions to recover from critical failures. Thus, the main contribution of this work is a solution to improve fault awareness and the analysis of the fault models in the system. In order to validate this solution, we performed complementary experiments in two irradiation facilities, comprehending atmospheric neutrons and a mixed-field environment, in which the system proved to be valuable for analyzing the radiation effects on the processor core and its peripherals. In these experiments, we were able to obtain a range of error reports that allowed us to gain a deeper understanding of the faults mechanisms, as well as improve the characterization of the SoC.

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Section: Methodsmentioning

confidence: 99%

Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip

et al. 2023

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“…While the FPGA configuration memory is flash-based, the Block RAMs (BRAMs) use an SRAM technology, and the Flip-Flops are D-type (DFF). We are using both BRAMS and DFFs in our design, which are susceptible to SEUs, as shown in the device characterization made in [17].…”

Section: Methodsmentioning

confidence: 99%

“…While on Board 0 these failures had fewer occurrences in the non-hardened implementation, Board 2 had fewer occurrences in the hardened implementation. Since the results look inconclusive at first analysis, we used the data from the device characterization made by the FPGA producer in [17] to help their interpretation. For this characterization, several Microsemi devices were tested against neutron radiation, in particular the Smartfusion2 family.…”

Section: Preliminary Soc Characterizationmentioning

confidence: 99%

“…We improved that processor to provide the means to use it as a microcontroller and evaluated its reliability features through two test campaigns in the ChipIr irradiation facility. Furthermore, for the implementation, we employed a flash-based FPGA innerly resilient to SEUs in the configuration memory [17] in order to focus on the microcontroller reliability features and filter the errors in the FPGA.…”

Section: Introductionmentioning

confidence: 99%

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Characterization of a RISC-V System-on-Chip under Neutron Radiation

Santos

Luza

Kastriotou

et al. 2021

2021 16th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Systems for harsh environments often use embedded processors for tasks that require reliability. However, harsh environments cause faulty behavior in electronics, which eventually lead to system failure. Therefore, embedded processors must use techniques to improve their reliability. In this context, this work presents the implementation and characterization of a RISC-V-based system-on-chip. We characterized our implementation by carrying out test campaigns at the ChipIr irradiation facility. This facility provides a beamline for testing electronics against neutrons, mimicking atmospheric-like environments. With this first test campaign, we identified the most critical parts of our system-on-chip and essential tips to improve the test effectiveness. In the second test campaign, we used an improved version of the system setup with higher reliability error observability features. The version embedding all the hardening techniques could correct or mitigate 98.1 % of the detected upsets under irradiation.

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“…Since the configuration memory is based on flash memory, it is more robust against single events, as shown by the manufacturer [24]. Although the enhanced reliability of the FPGA hosting the system under test, other internal components of interest are susceptible to SEEs, such as the Block RAMs (BRAMs), which are based on SRAM technology, and D-type Flip-Flops (DFFs), as shown in [25]. This setup is ideal for acquiring high-quality fault model data since only targeted structures are very sensitive to irradiation in an accelerated environment.…”

Section: B Experimental Setupmentioning

confidence: 99%

Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip

Santos

Mattos

Luza

et al. 2022

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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The radiation in harsh environments affects electronic systems, inducing permanent and temporary errors. These effects lead to unpredictable behaviors detrimental to critical applications and fail-safe systems. This work evaluates the reliability of a fault-tolerant RISC-V System-on-Chip (SoC) under atmospheric neutron irradiation in a particle accelerator. Prior work has analyzed the effectiveness of the hardening techniques of this SoC in simulation and provided a preliminary characterization in an irradiation facility. The applied hardening techniques showed a significant reliability improvement compared to the unhardened implementation of the SoC. The system executed a performance benchmark as workload, which finished correctly in most runs despite suffering from Single Event Effects (SEEs). This work presents a detailed analysis of the experimental results, reporting error rates and classification, extending the analysis given in previous works. Finally, a comprehensive discussion of implementation limitations and the proposition of further improvements are provided.

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Neutron SEE Testing of the 65nm SmartFusion2 Flash-Based FPGA

Cited by 13 publications

References 1 publication

Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip

Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip

Characterization of a RISC-V System-on-Chip under Neutron Radiation

Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip

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