Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip

Abstract

Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables the implementation and customization of the processor features to increase their reliability. Studies on hardened RISC-V processors facing harsh radiation environments apply fault tolerance techniques in the processor core and peripherals, exploiting system redundancies. In prior work, we present a hardened RISC-V System-on-Chip (SoC), which could detect and correct radiation-induced faults with limited fault awareness. Therefore, in this work, we propose solutions to extend the fault observability of the SoC implementation by providing error detection and monitoring. For this purpose, we introduce observation features in the redundant structures of the system, enabling the report of valuable information that supports enhanced radiation testing and support the application to perform actions to recover from critical failures. Thus, the main contribution of this work is a solution to improve fault awareness and the analysis of the fault models in the system. In order to validate this solution, we performed complementary experiments in two irradiation facilities, comprehending atmospheric neutrons and a mixed-field environment, in which the system proved to be valuable for analyzing the radiation effects on the processor core and its peripherals. In these experiments, we were able to obtain a range of error reports that allowed us to gain a deeper understanding of the faults mechanisms, as well as improve the characterization of the SoC.

Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments

“…In this experiment, we have two hardening configurations: baseline, with correction disabled, except the SECDED in the external memory, and hardened, with all the available protections enabled. We kept the SECDED enabled in the baseline to reduce the number of memory-related errors, as observed to be the most contributing error in all the previous characterizations, such as [11]. Moreover, these experiments consistently proved the importance of ECC in the system memory, leaving the opportunity for exploring other reliability aspects in this work.…”

“…The RISC-V System-on-Chip tested in this work (HARV-SoC) focuses on reliability for harsh environments [11]. The SoC is based on HARV (Hardened RISC-V) processor core [10], which applies hardening techniques on the architectural level to allow detecting, correcting, and reporting faults.…”

“…For this reason, we started the development of a RISC-V processor prospecting space applications in prior work [10]. Then, the processor was extended to become a robust SoC (known as HARV-SoC) with enhanced fault observability and monitoring for proper experimental validation, in which extensive tests were performed in various irradiation campaigns [11].…”

On-Chip Bus Protection against Soft Errors

“…On the other hand, the core should have access to information that errors were detected. If this is the case, a monitoring approach presented in [35] can be leveraged. The solution involves implementing an error handler component in the processor core that requests exception traps when detecting errors.…”