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Two Zn(ii)/Cd(ii) coordination polymers with different networks were constructed with mixed ligands. The former compound shows high catalytic activity for Knoevenagel condensation, and the latter compound can selectively recognize l-cysteine through the luminescence quenching effect.

A type of p-channel fin-on-insulator (FOI) FinFET charge trapping memory devices with HfO 2 charge trapping layer, Al 2 O 3 tunneling layer and blocking layers along with [TiN/W] metal gate (Metal/Al 2 O 3 /HfO 2 /Al 2 O 3 /Si, named as MAHAS in short) have been successfully fabricated. It is found that the new non-volatile memory, named in FOI-MAHAS memory shows better performance as compared with counterparts reported earlier owing to the adoption of p-type FOI channel and specific high-κ dielectrics. The static DC electrical characteristics of the fabricated memory devices including threshold voltage, subthreshold slope, gate breakdown voltage (BV g ), source-drain breakdown voltage (BV DS ) and memory characteristics such as program/erase (P/E) speed, memory window, endurance, and data retention at room temperature with different P/E approaches have been systematically investigated. A larger memory window, lower P/E voltages, improved P/E speed, as well as good data retention and endurance characteristics with band-to-band hot-electron (BBHE) programming are experimentally obtained. The developed p-channel FOI-MAHAS charge trapping memory is promising for the future nano-scaled NOR-type flash memory applications. It is well known that further scaling-down of the conventional bulk planar metal-oxide-semiconductor field-effect transistor (MOSFET) type NOR flash memory becomes very difficult because of the enhanced short-channel effect (SCE) induced by decreased gate control over channel region with the shrinkage of distance between source and drain. It is noteworthy that further scaling of planar NOR-type memory device faces the theoretical limit of source-drain breakdown voltage (BV DS ) which corresponds to the silicon (Si) and silicon dioxide (SiO 2 ) conduction band offset (3.2 eV). Thus, the scaled planar NOR-type flash memories with gate length (L g ) smaller than 100 nm are very difficult to fabricate.1-4 On the other hand, three-dimensional (3D) channel devices, such as fin field-effect transistors (FinFET) or fin-channel tri-gate (TG) device provide excellent SCE immunity thanks to the strong electrostatic controllability of the multiple gates. 5 Moreover, threshold voltage (V th ) variability in the FinFET or TG devices is much smaller than that in the conventional bulk planar MOSFETs because V th variation induced by the random dopant fluctuation (RDF) is negligible in FinFET or TG devices owing to the undoped fin-channels. Additionally, earlier study has shown that the electric field gets significantly enhanced in the curve part of the fin, thus the carrier injection rate from the channel gets substantially increased. As a result, the program and erase speeds of FinFET memory devices get obviously increased with respect to planer counterparts. [6][7][8][9] Recently a novel type of FinFET structure, named as fin-on-insulator (FOI) FinFET has been proposed.10,11 By adopting FOI structure, subsurface leakage paths in FinFETs are eliminated, the drain-induced barrier lowering (DIBL) is further reduced ...

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In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

A novel high-κ Al2O3/HfO2/Al2O3 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibits excellent program-erasable characteristics. A large memory window of ∼4 V, a small leakage current density of ∼2 × 10−6 Acm−2 at a gate voltage of 7 V, a high charge trapping density of 1.42 × 1013 cm−2 at a working voltage of ±10 V and good retention characteristics are observed. Furthermore, the programming ( at 10 V for 10 μs) and erasing speeds ( at −10 V for 10 μs) of the fabricated capacitor based on SiGe substrates are significantly improved as compared with counterparts reported earlier. It is concluded that the high-κ Al2O3/HfO2/Al2O3 nanolaminate charge trapping capacitor structure based on SiGe substrates is a promising candidate for future nano-scaled nonvolatile flash memory applications.