Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Abstract

A type of p-channel fin-on-insulator (FOI) FinFET charge trapping memory devices with HfO 2 charge trapping layer, Al 2 O 3 tunneling layer and blocking layers along with [TiN/W] metal gate (Metal/Al 2 O 3 /HfO 2 /Al 2 O 3 /Si, named as MAHAS in short) have been successfully fabricated. It is found that the new non-volatile memory, named in FOI-MAHAS memory shows better performance as compared with counterparts reported earlier owing to the adoption of p-type FOI channel and specific high-κ dielectrics. The static DC electrical characteristics of the fabricated memory devices including threshold voltage, subthreshold slope, gate breakdown voltage (BV g ), source-drain breakdown voltage (BV DS ) and memory characteristics such as program/erase (P/E) speed, memory window, endurance, and data retention at room temperature with different P/E approaches have been systematically investigated. A larger memory window, lower P/E voltages, improved P/E speed, as well as good data retention and endurance characteristics with band-to-band hot-electron (BBHE) programming are experimentally obtained. The developed p-channel FOI-MAHAS charge trapping memory is promising for the future nano-scaled NOR-type flash memory applications. It is well known that further scaling-down of the conventional bulk planar metal-oxide-semiconductor field-effect transistor (MOSFET) type NOR flash memory becomes very difficult because of the enhanced short-channel effect (SCE) induced by decreased gate control over channel region with the shrinkage of distance between source and drain. It is noteworthy that further scaling of planar NOR-type memory device faces the theoretical limit of source-drain breakdown voltage (BV DS ) which corresponds to the silicon (Si) and silicon dioxide (SiO 2 ) conduction band offset (3.2 eV). Thus, the scaled planar NOR-type flash memories with gate length (L g ) smaller than 100 nm are very difficult to fabricate.1-4 On the other hand, three-dimensional (3D) channel devices, such as fin field-effect transistors (FinFET) or fin-channel tri-gate (TG) device provide excellent SCE immunity thanks to the strong electrostatic controllability of the multiple gates. 5 Moreover, threshold voltage (V th ) variability in the FinFET or TG devices is much smaller than that in the conventional bulk planar MOSFETs because V th variation induced by the random dopant fluctuation (RDF) is negligible in FinFET or TG devices owing to the undoped fin-channels. Additionally, earlier study has shown that the electric field gets significantly enhanced in the curve part of the fin, thus the carrier injection rate from the channel gets substantially increased. As a result, the program and erase speeds of FinFET memory devices get obviously increased with respect to planer counterparts. [6][7][8][9] Recently a novel type of FinFET structure, named as fin-on-insulator (FOI) FinFET has been proposed.10,11 By adopting FOI structure, subsurface leakage paths in FinFETs are eliminated, the drain-induced barrier lowering (DIBL) is further reduced ...

Large memory window with low operating voltages using Hf 1.5 Gd 2 O 6 charge trapping layer and thin MoS 2 channel

“…Benchmarking plot of MW of HfGdO‐based CTMs realized in this work and the reported charge trap memories [14–18]. The various structures of different CTMs are shown in the figure as channel materials/charge trapping materials…”

“…The transfer curve from –1 to +1 V is defined as an original transfer curve for the following measurements. The quantity of charges stored in the charge trapping layer can be evaluated from the following expression [15]: where e is the electron charge, ΔV is the V TH movement from the original state to the negative or the positive direction, C HfGdO‐SiO2 = Ԑ 0 Ԑ SiO2 / d SiO2 is the capacitance between the HfGdO film and the back gate. The estimated density of stored charges under gate voltage range of 6 V is about 3.9 × 10 13 cm −2 , which shows that the HfGdO film can supply a high density of electron traps [19].…”

State of the Art and Future Perspectives in Advanced CMOS Technology

“…As a result, the most promising transistor architectures may be fin-on-insulator (FOI) Fin Field-Effect Transistor (FinFET) [ 8 , 9 , 10 , 11 ], scalloped fin FinFET [ 12 ], and NW field effect transistors (FETs) [ 13 , 14 , 15 ]. These new transistor designs have shown better control of short channel effects (SCEs), low leakage junctions, and high carrier mobility.…”

“…Figure11. Illustration of the hierarchy of technology computer-aided design (TCAD) device models[64].…”

Miniaturization of CMOS

“…Thus, new device structures, new materials, and new integration approaches have to provide new solutions. Therefore, novel promising device architectures like fin-on-insulator (FOI) FinFET [8,9,10,11], scalloped fin FinFET [12], nanowire (NW) FETs, and the stacked NW device [13,14,15] have demonstrated great improvement for short channel effects (SCEs), leakage control, and higher electron and whole mobility. The fin-on-insulator (FOI) FinFET, fabricated on the bulk Si substrate with a special process takes both advantages of bulk FinFET and SOI technologies.…”