Miniaturization of CMOS

Radamson, Henry H.; He, Xiaobin; Zhang, Qingzhu; Liu, Jinbiao; Cui, Hushan; Xiang, Jinjuan; Kong, Zhenzhen; Xiong, Wentao; Li, Junjie; Gao, Jianfeng; Yang, Hong; Gu, Shenyan; Zhao, Xu; Du, Yong; Yu, Jiahan; Wang, Guilei

doi:10.3390/mi10050293

Cited by 88 publications

(57 citation statements)

References 241 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Comparing with remote plasma and QALE, the selectivity to SiO2 is lower, but it has obvious advantages in etching anisotropy, which is crucial to control the accuracy of the final thickness of inner spacer. 3 Data of special method-typical remote downstream plasma 4 Data of special method-typical quasi-atomic layer etching 5 Related data are unknown…”

Section: Effect Of Pressure On Inner Spacer Etchingmentioning

confidence: 99%

See 1 more Smart Citation

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Zhou

et al. 2020

Nanomaterials

Self Cite

View full text Add to dashboard Cite

Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

show abstract

Section: Effect Of Pressure On Inner Spacer Etchingmentioning

confidence: 99%

“…3 Data of special method-typical remote downstream plasma. 4 Data of special method-typical quasi-atomic layer etching. 5 Related data are unknown…”

Section: Materials Quality and Interface Analysismentioning

confidence: 99%

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Zhou

et al. 2020

Nanomaterials

Self Cite

View full text Add to dashboard Cite

show abstract

“…Furthermore, the rigid polymers used in previous studies, such as SU-8 photoresist or epoxy resin chosen for their high chemical resistance, often do not provide a simple way to retrieve the chips after post-processing. In particular, as one moves in the future towards ever smaller chips such as the 22-nm transistor node and below [ 31 , 32 ], the smaller die or contact pad size is likely to affect the process yield as finished chips are fragile and difficult to handle, especially when the silicon chip is thinned to around 30 μm, making any post-CMOS process extremely challenging.…”

Section: Introductionmentioning

confidence: 99%

A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors

et al. 2020

View full text Add to dashboard Cite

Implantable active electronic microchips are being developed as multinode in-body sensors and actuators. There is a need to develop high throughput microfabrication techniques applicable to complementary metal–oxide–semiconductor (CMOS)-based silicon electronics in order to process bare dies from a foundry to physiologically compatible implant ensembles. Post-processing of a miniature CMOS chip by usual methods is challenging as the typically sub-mm size small dies are hard to handle and not readily compatible with the standard microfabrication, e.g., photolithography. Here, we present a soft material-based, low chemical and mechanical stress, scalable microchip post-CMOS processing method that enables photolithography and electron-beam deposition on hundreds of micrometers scale dies. The technique builds on the use of a polydimethylsiloxane (PDMS) carrier substrate, in which the CMOS chips were embedded and precisely aligned, thereby enabling batch post-processing without complication from additional micromachining or chip treatments. We have demonstrated our technique with 650 μm × 650 μm and 280 μm × 280 μm chips, designed for electrophysiological neural recording and microstimulation implants by monolithic integration of patterned gold and PEDOT:PSS electrodes on the chips and assessed their electrical properties. The functionality of the post-processed chips was verified in saline, and ex vivo experiments using wireless power and data link, to demonstrate the recording and stimulation performance of the microscale electrode interfaces.

show abstract

“…Over the last 50 years, there has been a development in the semiconductor industry, primarily based on Si substrate for fabricating integrated circuits such as complementary metal oxide semiconductor (CMOS) devices [1]. Subsequently, due to its favorable published Young's modulus value of 130 GPa for (100)-oriented Si [2], low thermal coefficient of expansion of 2.56 × 10 −6 K −1 , and high thermal conductivity of 157 W•m −1 •K −1 , Si has also been used to fabricate a large variety of microelectromechanical systems (MEMS) [3,4].…”

Section: Introductionmentioning

confidence: 99%

Infinite Selectivity of Wet SiO2 Etching in Respect to Al

et al. 2020

View full text Add to dashboard Cite

We propose and demonstrate an unconventional method suitable for releasing microelectromechanical systems devices containing an Al layer by wet etching using SiO2 as a sacrificial layer. We used 48% HF solution in combination with 20% oleum to keep the HF solution water-free and thus to prevent attack of the Al layer, achieving an outstanding etch rate of thermally grown SiO2 of ≈1 µm·min−1. We also verified that this etching solution only minimally affected the Al layer, as the chip immersion for ≈9 min increased the Al layer sheet resistance by only ≈7.6%. The proposed etching method was performed in an ordinary fume hood in a polytetrafluorethylene beaker at elevated temperature of ≈70 °C using water bath on a hotplate. It allowed removal of the SiO2 sacrificial layer in the presence of Al without the necessity of handling highly toxic HF gas.

show abstract

Miniaturization of CMOS

Cited by 88 publications

References 241 publications

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors

Infinite Selectivity of Wet SiO2 Etching in Respect to Al

Contact Info

Product

Resources

About