Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs

Abstract

A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

Epitaxial Growth of Ordered In-Plane Si and Ge Nanowires on Si (001)

“…Figure 2a shows trapezoidal Si NWs with a minimum width of approximately 20 nm, while still preserving good uniformity, as confirmed by the surface SEM images, as shown in Figure 2b. The average width of the neck is approximately 3 nm, as shown in the inset of Figure 2a, expected to be facilely isolated by thermal oxidation [23,24]. The lengths of NW arrays are defined ranging from 2 µm up to 2 mm, suggesting a large aspect ratio (length: width) of nearly 10 5 .…”

Temperature Dependent Characteristics and Electrostatic Threshold Voltage Tuning of Accumulated Body MOSFETs

“…Since the charges controlling the barrier height in MOSFETs are electrically isolated from the channel, there is no need for continuous charge injection from the control terminal, unlike BJTs. Ultra-thin-body silicon on insulator (SOI) [1]- [5], FinFET [6]- [9], tri-gate [10]- [15], gate-all-around [16]- [23] and multi-gate [24], [25] structures provide significant improvements in electrostatic control of the source-barrier in MOSFETs and suppress or eliminate the interface leakage currents [26]. Thin-body SOI and gate-all-around devices suffer from floating body effects [27], [28], where majority carriers trapped in the active region reduce the source-barrier (similar to charging of the base in BJTs) and cause soft errors.…”

“…The active regions of bulk MOSFETs have good electrical and thermal contact with the substrate, allowing for efficient charge and heat removal. Electrostatic control of the source-barrier using substrate/body [23], [29]- [36] or back-gate biasing [37]- [39] allows for dynamic control of threshold voltage. In the case of narrow channel devices, an independently controlled sidegate structure that surrounds the body of a bulk MOSFET can be used to accumulate the body of the device and increase electrical coupling of the body to the channel, increase the source barrier and suppress short-channel effects (Fig.…”

“…Transistors are thermal devices; the barrier height, the energy distribution of the carriers in the source and drain reservoirs and lifetime of trapped charges [46] depend on temperature. Carrier mobilities also increase with reduced temperature [23], [24], [47]- [49]. Hence, transistors can be operated with lower power and at a higher speed under lower temperatures.…”

“…Hence, transistors can be operated with lower power and at a higher speed under lower temperatures. While high temperature operation is necessary for certain applications [50]- [53], cryogenic operation of high-performance VLSI circuits has been considered for a long time [23], [24], [47]- [49], [54]- [58]. Recent advances and growing interest in quantum computing have also led to renewed interest in cryogenic electronics for peripheral circuitry.…”