Novel GAA Si Nanowire p-MOSFETs With Excellent Short-Channel Effect Immunity via an Advanced Forming Process

Zhang, Qingzhu; Meng, Lingkuan; Yao, Jiaxin; Li, Junjie; Wang, Guilei; Li, Yudong; Wu, Zhenhua; Xiong, Wenjing; Yang, Hong; Tu, Hailing; Li, Junfeng; Zhao, Chao; Wang, Wenwu; Ye, Tianchun

doi:10.1109/led.2018.2807389

Cited by 46 publications

(18 citation statements)

References 10 publications

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“…As compared to conventional TCAD framework, the physical level modeling has advantages that it captures the subband variations under strong confinement and considers multiple carrier scattering mechanisms, phonon scattering, and surface roughness scattering directly, rather than empirical mobility models. Overall verification of above physics-based models was shown in our previous work [19]- [20] by comparing with the measurement data of the in-house 5nm node SOI nanowire [21]. Furthermore, this validated TCAD framework can well reproduce the published data of the state-of-the-art 7-nm node FinFET [22] and fairly guarantee the accuracy of our SPICE model.…”

Section: Spice Model and Simulation Methodssupporting

confidence: 68%

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Huang

Zhu

et al. 2020

IEEE J. Electron Devices Soc.

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In this study, the negative DIBL (N-DIBL), negative differential resistance (NDR), and Miller effect of a negative capacitance nanowire filed-effect-transistor (negative capacitance (NC) NWFET) were analyzed by employing the custom-built SPICE model. In the simulation, the minimum subthreshold swing (SS) reduced to 40 mV/decade with negligible hysteresis, and the on-current amplified by approximately three times. The N-DIBL effect was analyzed by building a model, and the results indicated that the N-DIBL is negatively correlated with the SS. Hence, it is indispensable to make trade-offs between the N-DIBL and SS in NC NWFET applications. Moreover, the Miller effect of a NCFET-based inverter was investigated for the first time. The Miller effect of the NC NWFET-based inverter was considerably improved owing to a high on-current and negative internal gate voltage (when external gate voltage is set to 0V), which is beneficial for high-speed circuit building based on NC NWFETs. The overshoot of the NC NWFET-based inverter is ~43.1% less than that of the NWFET-based inverter, and the propagation delay of the NC NWFET-based inverter is ~73.1% less than that of the NWFET-based inverter at ferroelectric thickness TFE=3nm.

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Section: Spice Model and Simulation Methodssupporting

confidence: 68%

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Huang

Zhu

et al. 2020

IEEE J. Electron Devices Soc.

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“…Fig. 1 shows the overall verification of above physics-based models by comparing with the measurement data of the in-house 5nm node SOI nanowire [19]. Furthermore, this validated TCAD framework can well reproduce the published data of the state-of-the-art 7-nm node FinFET [20] and fairly guarantee the accuracy of our general compact model and 7-nm node ESD power clamp proposed in this work.…”

Section: Device Performance Analysis With Tcadsupporting

confidence: 56%

A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond

Huo

Huang

et al. 2020

IEEE J. Electron Devices Soc.

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This work presents a novel general compact model for 7-nm technology node devices like FinFETs as an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects. The general compact model exhibits efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control electrostatic discharge (ESD) power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for path-finding researches on 5-nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.

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“…It is very meaningful to understand the integration process of FinFET. In future, the next-generation devices, such as gate-all-around nanowire transistor or nanosheet FET, are still dependent on current FinFET integration flow [18,19].…”

Section: Finfet Integration Processmentioning

confidence: 99%

Advanced Transistor Process Technology from 22- to 14-nm Node

Yao¹

2018

Complementary Metal Oxide Semiconductor

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Transistor performance meets great technical challenges as the critical dimension (CD) shrinking beyond 32/28-nm nodes. A series of innovated process technologies such as high-k/metal gate, strain engineering, and 3D FinFET to overcome these challenges are reviewed in this chapter. The principle, developing route, and main prosperities of these technologies are systematically described with theoretical analysis and experimental results. Especially, the material choice, film stack design, and process flow integration approach with high-k/metal gate for sub-22-nm node is introduced; the film growth technique, process optimization, and flow integration method with advanced strain engineering are investigated; the architecture design, critical process definition, and integration scheme matching with traditional planar 2D transistor for 14-nm 3D FinFET are summarized.

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Novel GAA Si Nanowire p-MOSFETs With Excellent Short-Channel Effect Immunity via an Advanced Forming Process

Cited by 46 publications

References 10 publications

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond

Advanced Transistor Process Technology from 22- to 14-nm Node

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