Structural and electrical characteristics of epitaxial germanium (Ge) heterogeneously integrated on silicon (Si) via a composite, large bandgap AlAs/GaAs buffer are investigated. Electrical characteristics of N-type metal-oxide-semiconductor (MOS) capacitors, fabricated from the aforementioned material stack are then presented. Simulated and experimental X-ray rocking curves show distinct Ge, AlAs, and GaAs epilayer peaks. Moreover, secondary ion mass spectrometry, energy dispersive X-ray spectroscopy (EDS) profile, and EDS line profile suggest limited interdiffusion of the underlying buffer into the Ge layer, which is further indicative of the successful growth of device-quality epitaxial Ge layer. The Ge MOS capacitor devices demonstrated low frequency dispersion of 1.80% per decade, low frequency-dependent flat-band voltage, V FB , shift of 153 mV, efficient Fermi level movement, and limited C-V stretch out. Low interface state density (D it ) from 8.55 × 10 11 to 1.09 × 10 12 cm −2 eV −1 is indicative of a high-quality oxide/Ge heterointerface, an effective electrical passivation of the Ge surface, and a Ge epitaxy with minimal defects. These superior electrical and material characteristics suggest the feasibility of utilizing large bandgap III-V buffers in the heterointegration of high-mobility channel materials on Si for future high-speed complementary metal-oxide semiconductor logic applications.INDEX TERMS Germanium (Ge), heteroepitaxy, metal-oxide semiconductor (MOS) devices, silicon (Si), III-V materials.

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In this work, an in situ SiO 2 passivation technique using atomic layer deposition (ALD) during the growth of gate dielectric TaSiO x on solid-source molecular beam epitaxy grown (100)In x Ga 1– x As and (110)In x Ga 1– x As on InP substrates is reported. X-ray reciprocal space mapping demonstrated quasi-lattice matched In x Ga 1– x As epitaxy on crystallographically oriented InP substrates. Cross-sectional transmission electron microscopy revealed sharp heterointerfaces between ALD TaSiO x and (100) and (110)In x Ga 1– x As epilayers, wherein the presence of a consistent growth of an ∼0.8 nm intentionally formed SiO 2 interfacial passivating layer (IPL) is also observed on each of (100) and (110)In x Ga 1– x As. X-ray photoelectron spectroscopy (XPS) revealed the incorporation of SiO 2 in the composite TaSiO x , and valence band offset (Δ E V ) values for TaSiO x relative to (100) and (110)In x Ga 1– x As orientations of 2.52 ± 0.05 and 2.65 ± 0.05 eV, respectively, were extracted. The conduction band offset (Δ E C ) was calculated to be 1.3 ± 0.1 eV for (100)In x Ga 1– x As and 1.43 ± 0.1 eV for (110)In x Ga 1– x As, using TaSiO x band gap values of 4.60 and 4.82 eV, respectively, determined from the fitted O 1s XPS loss spectra, and the literature-reported composition-dependent In x Ga 1– x As band gap. The in situ passivation of In x Ga 1– x As using SiO 2 IPL during ALD of TaSiO x and the relatively large Δ E V and Δ E C values reported in this work are expected to aid in the future development of thermodynamically stable high-κ gate dielectrics on In x Ga 1– x As with reduced gate leakage, particularly under low-power device operation.

Broken-gap InAs/GaSb strain balanced multilayer structures were grown by molecular beam epitaxy (MBE), and their structural, morphological, and band alignment properties were analyzed. Precise shutter sequence during the MBE growth process, enable to achieve the strain balanced structure. Cross-sectional transmission electron microscopy exhibited sharp heterointerfaces, and the lattice line extended from the top GaSb layer to the bottom InAs layer. X-ray analysis further confirmed a strain balanced InAs/GaSb multilayer structure. A smooth surface morphology with surface roughness of ∼0.5 nm was demonstrated. The effective barrier height -0.15 eV at the GaSb/InAs heterointerface was determined by X-ray photoelectron spectroscopy, and it was further corroborated by simulation. These results are important to demonstrate desirable characteristics of mixed As/Sb material systems for high-performance and low-power tunnel field-effect transistor applications.

Mixed-anion, GaAs1-ySby metamorphic materials with tunable antimony (Sb) compositions extending from 0 to 100%, grown by solid source molecular beam epitaxy (MBE), were used to investigate the evolution of interfacial chemistry under different passivation conditions. X-ray photoelectron spectroscopy (XPS) was used to determine the change in chemical state progression as a function of surface preclean and passivation, as well as the valence band offsets, conduction band offsets, energy band parameters, and bandgap of atomic layer deposited Al2O3 on GaAs1-ySby for the first time, which is further corroborated by X-ray analysis and cross-sectional transmission electron microscopy. Detailed XPS analysis revealed that the near midpoint composition, GaAs0.45Sb0.55, passivation scheme exhibits a GaAs-like surface, and that precleaning by HCl and (NH4)2S passivation are mandatory to remove native oxides from the surface of GaAsSb. The valence band offsets, ΔEv, were determined from the difference in the core level to the valence band maximum binding energy of GaAs1-ySby. A valence band offset of >2 eV for all Sb compositions was found, indicating the potential of utilizing Al2O3 on GaAs1-ySby (0 ≤ y ≤ 1) for p-type metal-oxide-semiconductor (MOS) applications. Moreover, Al2O3 showed conduction band offset of ∼2 eV on GaAs1-ySby (0 ≤ y ≤ 1), suggesting Al2O3 dielectric can also be used for n-type MOS applications. The surface passivation of GaAs0.45Sb0.55 materials and the detailed band alignment analysis of Al2O3 high-κ dielectrics on tunable Sb composition, GaAs1-ySby materials, provides a pathway to utilize GaAsSb materials in future microelectronic and optoelectronic applications.

The indirect nature of silicon (Si) emission currently limits the monolithic integration of photonic circuitry with Si electronics. Approaches to circumvent the optical shortcomings of Si include band structure engineering via alloying (e.g., Si x Ge1–x–y Sn y ) and/or strain engineering of group IV materials (e.g., Ge). Although these methods enhance emission, many are incapable of realizing practical lasing structures because of poor optical and electrical confinement. Here, we report on strong optoelectronic confinement in a highly tensile-strained (ε) Ge/In0.26Al0.74As heterostructure as determined by X-ray photoemission spectroscopy (XPS). To this end, an ultrathin (∼10 nm) ε-Ge epilayer was directly integrated onto the In0.26Al0.74As stressor using an in situ, dual-chamber molecular beam epitaxy approach. Combining high-resolution X-ray diffraction and Raman spectroscopy, a strain state as high as ε ∼ 1.75% was demonstrated. Moreover, high-resolution transmission electron microscopy confirmed the highly ordered, pseudomorphic nature of the as-grown ε-Ge/In0.26Al0.74As heterostructure. The heterointerfacial electronic structure was likewise probed via XPS, revealing conduction- and valence band offsets (ΔE C and ΔE V) of 1.25 ± 0.1 and 0.56 ± 0.1 eV, respectively. Finally, we compare our empirical results with previously published first-principles calculations investigating the impact of heterointerfacial stoichiometry on the ε-Ge/In x Al1–x As energy band offset, demonstrating excellent agreement between experimental and theoretical results under an As0.5Ge0.5 interface stoichiometry exhibiting up to two monolayers of heterointerfacial As–Ge diffusion. Taken together, these findings reveal a new route toward the realization of on-Si photonics.

The work of J.-S. Liu and M. B. Clavel was supported in part by the National Science Foundation under Grant ECCS-1507950. ABSTRACT A novel, tunnel field-effect transistor (TFET)-based adiabatic logic (TBAL) circuit topology has been proposed, evaluated and benchmarked with several device architectures (planar MOSFET, FinFET, and TFET) and AL implementations (efficient charge recovery logic, 2N-2N2P, positive feedback adiabatic logic) operating in the ultra-low voltage (0.3 V ≥ V DD ≤ 0.6 V) regime. By incorporating adiabatic logic functionality into standard combinational logic, an 80% reduction in energy/cycle was achieved. A further 80% reduction in energy/cycle was demonstrated by utilizing near broken-gap TFET devices and simultaneous scaling of supply voltage to 0.3 V, resulting in a 96% reduction in energy/cycle as compared to conventional Si CMOS. Extension of operating frequency beyond 10 MHz, coupled with sub-threshold circuit operation, shows the feasibility of TBAL for energy-efficient Internet of Things applications.