TBAL: Tunnel FET-Based Adiabatic Logic for Energy-Efficient, Ultra-Low Voltage IoT Applications

Liu, Jheng-Sin; Clavel, Michael; Hudait, Mantu K.

doi:10.1109/jeds.2019.2891204

Cited by 20 publications

(10 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Among several proposed TFETs, III-V TFETs appear more promising because of higher ON current [20][21][22]. In III-V TFETs, InAs homo-junction and GaSb-InAs hetero-junction TFETs exhibit superior performance [31,32].…”

Section: Device Descriptionmentioning

confidence: 99%

“…Among several post‐CMOS devices, TFETs have emerged as a promising device candidate for future low energy electronic circuit design [20, 21]. TFET with its band‐to‐band tunnelling mechanism achieves a high I ON / I OFF ratio and steep subthreshold swing (SS) (<60 mV/dec) at lower supply voltages [22, 23]. In the recent experimental demonstration, III–V heterojunction TFET achieved 92 µA/µm ON current with 48 mV SS at a supply voltage of 0.5 V [24].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator

Japa

Majumder

Sahoo

et al. 2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS-based DPA countermeasures resulted in high area overhead and performance degradation. This study presents low area overhead DPA countermeasure exploring tunnel field effect transistors (TFET) based random number generator (RNG). TFET exhibits significant p-in forward current with an increase in negative drain-to-source voltage bias. It is demonstrated that TFET transmission gate exhibits unconventional behaviour due to p-in forward current of the device. Leveraging this behaviour TFET RNG is designed that extracts random bits from delay variations of the TFET ring oscillator. The proposed TFET RNG achieves low area overhead when compared with the baseline CMOS designs. The proposed DPA countermeasure is demonstrated by integrating the original TFET substitution box (S-box) and TFET RNG. The proposed architecture is found to be resilient to DPA attack and the area overhead of single S-box and Advanced Encryption Standard AES is as low as 12 and 5%, respectively. Apart from low area overhead, the TFET designs with inherent device characteristics show high robustness against reverse engineering attacks which provide a higher level of security to TFET-based circuits and systems.

show abstract

Section: Device Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator

Japa

Majumder

Sahoo

et al. 2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…The disadvantage of higher energy and power dissipation is that the circuits require more expensive packaging and expansive cooling technology which decreases reliability also increases cost. As the level of clock frequency and on-chip integration will continue to grow as per the demands of faster computing, the energy and power dissipation of these high performance circuits is a perilous design issue [2]. To achieve Tera Instructions per seconds (TIPS) high end microprocessor employ billions of transistor on chip at clock rates over 30 GHz, with this rate of speed power dissipation of circuit is projected to extend to thousands of watts.…”

Section: Introductionmentioning

confidence: 99%

“…Considering one full cycle of operation from VDD to GND and from GND to VDD, the process of charging the capacitor draws energy from the power supply which is equal to C . (VDD ) 2 . Half power is stored in capacitor while half is dissipated in pMOS, during operation ground to VDD, the capacitance is discharged and energy is dissipated in nMOS.…”

Section: Introductionmentioning

confidence: 99%

Design and Power Dissipation Consideration of PFAL CMOS V/S Conventional CMOS Based 2:1 Multiplexer and Full Adder

Sharma¹,

Pandey

Palta³

et al. 2021

Silicon

View full text Add to dashboard Cite

Increasing transistor switching time and rising count of transistors integrated over a chip area has given a high pace in computing systems by several orders of magnitude. With the integration of circuits, number of gates and transistors are increasing per chip area. CMOS Logic family is preferred due to its performance and impeccable noise margins over other families. However with integration in every digital circuit, the energy due to switching of gate doesn't decrease at same rate as gates are increased per chip area. Due to this, power dissipation becomes significant and also reduction of heat becomes more complicated and expensive. In CMOS based circuits dynamic power requirement is becoming major concern in digital circuits. In this paper, the work is focused on reducing the power dissipation in circuits which is increasing with down scaling of circuits. The work is done on 2:1 multiplexer and full adder circuit. Adiabatic logic with positive feedback (PFAL) is applied to redesign the circuit with input power taken as sinusoidal source of 3.3 V and analysis is done for power dissipation between conventional CMOS and PFAL based CMOS circuits. In comparison with the conventional CMOS 2:1 multiplexer circuit, the designed PFAL CMOS 2:1 multiplexer circuit has less power dissipation as 80.871 picoWatts while conventional CMOS circuit has 6.9090 nanoWatts with the same behavior of circuit. Also for full adder conventional CMOS circuit have 48.0452 picoWatts while PFAL based full adder has 3.9089 picoWatts.

show abstract

“…The continuous reduction in device size leads to exponential increase in the leakage power due to Short Channel Effects. At the device level several alternative structures like CNTFET [9], FinFET and TFET [10] are proposed in place of conventional MOSFET. The use of FinFET as an alternative to CMOS further improves the energy recovery of the adiabatic logic.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Adiabatic Vedic Multipliers

Kaza¹

2021

TURCOMAT

View full text Add to dashboard Cite

Energy dissipation and reliability are the two important design constraints in the high performance processor design. With the advancements in the IC manufacturing and reduced feature sizes the energy dissipation increases in exponential manner at the lower technology nodes. So, there is a need to design energy-efficient and reliable circuits and systems. The reliability with temperature is also one of the major challenges in today’s smart systems as they are operated in harsh environments. Most of the works till date analyzed the reliability with respect to DC constraints. The basic operation in the high performance Digital Signal Processing (DSP) is the multiplication is used to simplify various operations like convolution, filtering and correlation. In this work, a Vedic multiplier with 4x4 size is implemented with FinFET based energy recovery Modified PFAL (MPFAL) logic at 45 nm technology node. The designed multiplier performance is analyzed and compared with our earlier work in terms of energy dissipation and delay. The results indicate a reduction of 55% in energy dissipation over ECRL based Vedic multiplier. Linear variation of power dissipation with temperature in the order of pW shows that design MPFAL Vedic muliplier is more reliable compared to CMOS multiplier.

show abstract

TBAL: Tunnel FET-Based Adiabatic Logic for Energy-Efficient, Ultra-Low Voltage IoT Applications

Cited by 20 publications

References 26 publications

Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator

Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator

Design and Power Dissipation Consideration of PFAL CMOS V/S Conventional CMOS Based 2:1 Multiplexer and Full Adder

Performance Analysis of Adiabatic Vedic Multipliers

Contact Info

Product

Resources

About