Performance Analysis of Adiabatic Vedic Multipliers

Abstract

Energy dissipation and reliability are the two important design constraints in the high performance processor design. With the advancements in the IC manufacturing and reduced feature sizes the energy dissipation increases in exponential manner at the lower technology nodes. So, there is a need to design energy-efficient and reliable circuits and systems. The reliability with temperature is also one of the major challenges in today’s smart systems as they are operated in harsh environments. Most of the works till date analyzed the reliability with respect to DC constraints. The basic operation in the high performance Digital Signal Processing (DSP) is the multiplication is used to simplify various operations like convolution, filtering and correlation. In this work, a Vedic multiplier with 4x4 size is implemented with FinFET based energy recovery Modified PFAL (MPFAL) logic at 45 nm technology node. The designed multiplier performance is analyzed and compared with our earlier work in terms of energy dissipation and delay. The results indicate a reduction of 55% in energy dissipation over ECRL based Vedic multiplier. Linear variation of power dissipation with temperature in the order of pW shows that design MPFAL Vedic muliplier is more reliable compared to CMOS multiplier.