Design and Power Dissipation Consideration of PFAL CMOS V/S Conventional CMOS Based 2:1 Multiplexer and Full Adder

Sharma, Manvinder; Pandey, Digvijay; Palta, Pankaj; Pandey, Binay Kumar

doi:10.1007/s12633-021-01221-1

Cited by 28 publications

(4 citation statements)

References 28 publications

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“…Conversely, a decrease in the WP/LP ratio by 1 results in a decrease in Idpeak, and the curve shifts left, in contrast to the behavior of the NMOS transistor. This observation underscores the inverse relationship between the WP/LP ratio and the behavior of PMOS and NMOS transistors [38].…”

Section: Change In Pmosmentioning

confidence: 57%

Investigation of Temperature and Channel Dimension Effects on CMOS Circuit Performance

Messai,

Brahimi,

Saidani

et al. 2024

East Eur. J. Phys.

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This paper presents the impact of temperature variations and alterations in transistor channel dimensions on CMOS (Complementary Metal-Oxide-Semiconductor) circuit technology. To facilitate this investigation, we first identified critical parameters characterizing the device's performance, which could exhibit susceptibility to these influences. The analysis encompassed critical metrics such as the transfer characteristic, drain current, logic levels, inflection points, and truncation points. These parameters enabled us to validate the results obtained from the PSPICE simulator, which demonstrated unequivocal effectiveness. Notably, our simulation results unveiled significant effects resulting from a wide temperature range spanning from -100°C to 270°C, offering valuable in-sights into thermal-induced failures. Additionally, the influence of channel dimension changes on factors like drain current and transfer characteristics, as well as temporal parameters including signal propagation delay and rise and fall times, were meticulously examined and appreciated.

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Section: Change In Pmosmentioning

confidence: 57%

Investigation of Temperature and Channel Dimension Effects on CMOS Circuit Performance

Messai,

Brahimi,

Saidani

et al. 2024

East Eur. J. Phys.

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“…The selection lines S1, and S0 select which inputs should be relayed to the output. Every input has a potential generated by Equation ( 1) [38].…”

Section: Design a 4 × 1 Multiplexer Using N-pass Time Division Techni...mentioning

confidence: 99%

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques

Tamilarasan,

Duraisamy,

Elangovan

et al. 2023

Micromachines

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Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of −68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of −5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

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“…In the active mode of sleepy stack transistor, turn on all the sleep transistors. The circuit delay can be potentially reduced in this mode [32]. Faster switching time is achieved in the active mode since all the sleep transistors are turned on.…”

Section: Sleepy Stack Structurementioning

confidence: 99%

Implementation and Modeling of Low Power Sleepy Stack Sram

Kakkar¹

2022

joas

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For the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However, sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

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Design and Power Dissipation Consideration of PFAL CMOS V/S Conventional CMOS Based 2:1 Multiplexer and Full Adder

Cited by 28 publications

References 28 publications

Investigation of Temperature and Channel Dimension Effects on CMOS Circuit Performance

Investigation of Temperature and Channel Dimension Effects on CMOS Circuit Performance

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques

Implementation and Modeling of Low Power Sleepy Stack Sram

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