Implementation and Modeling of Low Power Sleepy Stack Sram

Abstract

For the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However, sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

Design of 4-bit absolute value detector with low energy

“…The energy efficiency is remarkable at 0.6 pJ per cycle, an important parameter for circuits that require high performance while consuming little power. The proposed AVD circuit performance is simulated in a conventional 45nm CMOS technology, which is extensively utilized in the semiconductor industry [15]. A circuit is a great option for various DSP applications because, as demonstrated by the simulation results, it offers high precision and a short response time.…”