An Energy-Efficient Tensile-Strained Ge/InGaAs TFET 7T SRAM Cell Architecture for Ultralow-Voltage Applications

Liu, Jheng-Sin; Clavel, Michael; Hudait, Mantu K.

doi:10.1109/ted.2017.2675364

Cited by 37 publications

(24 citation statements)

References 9 publications

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“…Liu et al [20] have present a tensile-strained Ge/InGaAs TFET-based SRAM circuit utilizing a few access schemes and research the cell access design impact on static and dynamic performance. SRAM cells utilizing outward access transistors exhibit wide read and write static noise margins, yet suffer from increased read delay times.…”

Section: Problem Methodologymentioning

confidence: 99%

“…In this way, it is exceptionally appropriate to design SRAM cell with limited read delay time and low power consumption. The proposed design is tested with the SRAM cell and performance is contrasted with the tensile-strained Ge/InGaAs TFET-based SRAM [20] in terms of power and delay.…”

Section: Problem Methodologymentioning

confidence: 99%

“…Since the core of the cell structure is similar in all the four SRAM cells during write operation, while analyzing the write access time is almost same for all SRAM cells. Table 2 clearly depicts the read delay of the proposed SRAM-SDAC cell is exceptionally lower than SRAM cell in [20] for all strain levels.…”

Section: Delay Comparisonmentioning

confidence: 97%

“…The actual read delay will be even more as it uses single ended read. Table 1 clearly portrays the read delay of the proposed SRAM-SDAC cell is lower than SRAM cell in [20] for all strain levels. Write delay is analyzed from the writing 'Low' at node Q is the time required for node Q to fall to 10% of its initial voltage for 'High' after the WL is turned on during a write operation.…”

Section: Delay Comparisonmentioning

confidence: 99%

“…The performance correlation of proposed SRAM cell is contrasted with distinctive SRAM cells, for example, outward, CMOS, hybrid and inward [20] with the operating frequency of 0.3 and 0.6 V in terms of RSNM and WSNM. The result esteems are plotted in Fig.…”

Section: Impact Of Snm In Read and Write Operationmentioning

confidence: 99%

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Low Power Strain and Dimension Aware SRAM Cell Design Using a New Tunnel FET and Domino Independent Logic

Reddy¹,

Jayasree²

2018

IJIES

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Mechanical strain and dimension in silicon leads to band splitting and alters the effective mass which results in carrier mobility changes. Induced strain and dimension effects on channel can be either "tensile" or "compressive". NMOS and PMOS devices have different desired strain and dimension types in the longitudinal, lateral and Si-depth dimensions. The small band gap tensile strained silicon is more compatible than conventional silicon processing for low power circuit design. In this paper, we propose strain and dimension aware circuit (SDAC) design using new physics model and domino clock and input dependent (d-INDEP) logic. In SDAC design, an optimal depleted strained TFET physics model is used to improve the on-current and steep sub-threshold swing, which are main cause of strain and dimension effects. The performance of any logic design is reduced by increasing leakage current and variability of parameters, which affects the power consumption problem. The problem is overcome by the d-INDEP logic that reduces leakage current as well as affected power without extra logics. The proposed physics and low power logic is tested with SRAM cell and simulated in HSPICE tool. The simulation result shows the effectiveness of proposed SDAC design in terms of power and delay.

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Section: Problem Methodologymentioning

confidence: 99%

Section: Problem Methodologymentioning

confidence: 99%

Section: Delay Comparisonmentioning

confidence: 97%

Section: Delay Comparisonmentioning

confidence: 99%

Section: Impact Of Snm In Read and Write Operationmentioning

confidence: 99%

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