Tunnel FET Based SRAM Cells – A Comparative Review

Rasheed, Gadarapulla; Sridevi, Sriadibhatla

doi:10.1007/978-981-16-5048-2_17

Cited by 8 publications

(1 citation statement)

References 34 publications

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“…In particular, the uncontrollable forward p-i-n current grows rapidly with the V SD increasing, which will limit its application in circuits [13]. Many studies have been conducted on the TFET applications in SRAM design [13][14][15][16][17][18][19][20][21][22][23], but a series of problems are still not resolved, especially the following two problems: 1. The problem of large static power consumption caused by forward p-i-n current in the transmission transistor.…”

Section: Introductionmentioning

confidence: 99%

Tunnel FET and MOSFET Hybrid Integrated 9T SRAM with Data-Aware Write Technique for Ultra-Low Power Applications

Dong

et al. 2022

Electronics

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In this paper, a Tunnel FETs (TFETs) and MOSFETs hybrid integrated 9T SRAM (HI-9T) with data-aware write technique is proposed. This structure solves the problem of excessive static power consumption caused by forward p-i-n current in the conventional 7T TFET SRAM (CV-7T), and the problem of weakened writing ability caused by the use of the TFET-stacked structure of the most advanced combined access 10T TFET SRAM (CA-10T). The simulation results demonstrate that the static power consumption of HI-9T is reduced by three orders of magnitude compared with CV-7T at a 0.6 V supply voltage and the ability to maintain data is more stable. Compared with CA-10T, the write margin (WM) of HI-9T is increased by about 2.4 times and the write latency is reduced by 54.8% at 0.5 V supply voltage. HI-9T still has good writing ability under the 0.6 V supply voltage and the CA-10T cannot write normally. Therefore, HI-9T has good overall performance and is more advantageous in ultra-low power applications.

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