Tunnel FET and MOSFET Hybrid Integrated 9T SRAM with Data-Aware Write Technique for Ultra-Low Power Applications

Abstract

In this paper, a Tunnel FETs (TFETs) and MOSFETs hybrid integrated 9T SRAM (HI-9T) with data-aware write technique is proposed. This structure solves the problem of excessive static power consumption caused by forward p-i-n current in the conventional 7T TFET SRAM (CV-7T), and the problem of weakened writing ability caused by the use of the TFET-stacked structure of the most advanced combined access 10T TFET SRAM (CA-10T). The simulation results demonstrate that the static power consumption of HI-9T is reduced by three orders of magnitude compared with CV-7T at a 0.6 V supply voltage and the ability to maintain data is more stable. Compared with CA-10T, the write margin (WM) of HI-9T is increased by about 2.4 times and the write latency is reduced by 54.8% at 0.5 V supply voltage. HI-9T still has good writing ability under the 0.6 V supply voltage and the CA-10T cannot write normally. Therefore, HI-9T has good overall performance and is more advantageous in ultra-low power applications.

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

“…The bitlines have a high value of the capacitive load, which in turn offers RC delays. The recent SRAM designs [ 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ] reported depict the novel device architectures of 6T SRAM with FinFET, Memristor, and Junctionless TFETs, to claim it to be a low-power device. Here, with our proposed sense amplifier design, the power reduction techniques like negative wordline and source biasing were combined and utilized.…”