Heteroepitaxial Ge MOS Devices on Si Using Composite AlAs/GaAs Buffer

Abstract

Structural and electrical characteristics of epitaxial germanium (Ge) heterogeneously integrated on silicon (Si) via a composite, large bandgap AlAs/GaAs buffer are investigated. Electrical characteristics of N-type metal-oxide-semiconductor (MOS) capacitors, fabricated from the aforementioned material stack are then presented. Simulated and experimental X-ray rocking curves show distinct Ge, AlAs, and GaAs epilayer peaks. Moreover, secondary ion mass spectrometry, energy dispersive X-ray spectroscopy (EDS) profile, and EDS line profile suggest limited interdiffusion of the underlying buffer into the Ge layer, which is further indicative of the successful growth of device-quality epitaxial Ge layer. The Ge MOS capacitor devices demonstrated low frequency dispersion of 1.80% per decade, low frequency-dependent flat-band voltage, V FB , shift of 153 mV, efficient Fermi level movement, and limited C-V stretch out. Low interface state density (D it ) from 8.55 × 10 11 to 1.09 × 10 12 cm −2 eV −1 is indicative of a high-quality oxide/Ge heterointerface, an effective electrical passivation of the Ge surface, and a Ge epitaxy with minimal defects. These superior electrical and material characteristics suggest the feasibility of utilizing large bandgap III-V buffers in the heterointegration of high-mobility channel materials on Si for future high-speed complementary metal-oxide semiconductor logic applications.INDEX TERMS Germanium (Ge), heteroepitaxy, metal-oxide semiconductor (MOS) devices, silicon (Si), III-V materials.

Heterogeneously-Grown Tunable Tensile Strained Germanium on Silicon for Photonic Devices

“…EDS is a powerful technique that has been extensively used for the analysis of the structural and chemical modulation of nanoscale heterostructures and multilayer heterostructures. 41 Figure 7b shows the elemental mapping of the ε-Ge/In 0.11 Ga 0.89 As structure where the Ge layer (green) was found to be uniformly distributed and the In (blue) exhibits a variable composition, as expected in the linearly graded In x Ga 1−x As buffer layer, in addition to the composition profile of Si (red). The EDS analysis exhibits a uniform and sharp heterointerface between the ε-Ge and the In 0.11 Ga 0.89 As layer, with no apparent interdiffusion across any of the structure's heterointerfaces despite the increased thermal budget as a result of experiencing extended growth temperature conditions during the strained layer epitaxy of Ge.…”

First-Principles Calculations of Band Offsets at Heterovalent ε - Ge/InxAl1−xAsGreene‐Diniz1, Grüning2 2018Phys. Rev. Applied3100View full textAdd to dashboardCite

“…4), which is consistent with previous experimental reports of interface abruptness in comparable heterostructures. 2,3 However, these interfacial configurations are unrealistic, and for heterostructures present in experimental samples, interfacial configurations involving mixed depths of diffusing species throughout the interfacial region are much more likely to occur. As a first approximation, this can be investigated by linearly varying the stoichiometric balance of atoms between adjacent MIMLs (while always maintaining charge neutral configurations) near the interface.…”

“…The interface of tensile strained germanium (ε-Ge) grown on III-V substrates is currently being considered as the working tunnel-barrier in the channel of future highperformance and low-power consumption tunnel fieldeffect transistors (TFETs). [1][2][3] These devices take advantage of band-to-band tunneling of charge carriers between the source and drain, and as a result, can overcome the limit for the subthreshold slope of thermionic devices, 4 thereby simultaneously improving the transistor switching speed (performance) and I ON /I OFF current ratio (power efficiency). Concurrently, there is a large research effort dedicated to the integration of optical interconnects on a CMOS compatible platform, 5,6 allowing for highly efficient ultrafast inter-and intra-chip data communication.…”

Growth, structural, and electrical properties of germanium-on-silicon heterostructure by molecular beam epitaxy

“…Bulk Ge devices can be observed to benefit from the lowest D it due to the absence of lattice mismatch-induced dislocations propagating through to the inversion surface. From Figure 13, a representative D it value for Ge-on-Si MOSCAPs studied in this work can be found to be on par with that from other Ge devices integrated on Si via buffer techniques 7,10,44 or insulator layers. 47 Thus, the various electrical characteristics of Ge-on-Si MOS capacitors investigated here provides critical guidance in understanding the viability of high-mobility channel material directly integrated on Si, for low-voltage CMOS logic application.…”

“…The previously published data use a variety of gate oxides and substrates, which could affect both the reported D it and TDD values. 7,8,10,16,[43][44][45][46][47] Hence, the device structure is indicated alongside each data point. An interesting pattern emerges for Ge devices on Si using different epitaxial integration schemes and an Al 2 O 3 /GeO x gate stack: an almost linear increase in D it with increasing TDD.…”