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The authors have studied the interactions between implant defects and phosphorus diffusion in crystalline silicon. Defect engineering enables ultrashallow n+∕p junction formation using phosphorus, carbon, and germanium coimplants, and spike anneal. Their experimental data suggest that the positioning of a preamorphized layer using germanium implants plays an important role in phosphorus diffusion. They find that extending the overlap of germanium preamorphization and carbon profiles results in greater reduction of phosphorus transient-enhanced diffusion by trapping more excess interstitials. This conclusion is consistent with the end-of-range defects calculated by Monte Carlo simulation and annealed carbon profiles.

Gate length of 1-μm enhancement-mode n-channel GaN MOSFET with MgO and hybrid MgO-TiO 2 stacked gate dielectrics were characterized. The leakage current of a stacked MgO and hybrid MgO-TiO 2 MOS capacitor can be as low as 6.2 × 10 −9 and 6.9 × 10 −9 A/cm 2 at ±1-V bias, respectively. Through a self-aligned process, superior I D -V D and I D -V G electrical characteristics of a MOSFET were obtained. The maximum drain current is 3.69 × 10 −5 A/μm at a gate voltage V g of 8 V and a drain voltage V D of 10 V. The subthreshold swing is 342 mV/dec, and the I ON /I OFF is 5.7 × 10 4 .

A complementary metal oxide semiconductor (CMOS)-compatible WO x based resistive memory has been developed. The WO x memory layer is made from rapid thermal oxidation of W plugs. The device performs excellent electrical properties. The switching speed is extremely fast ($2 ns) and the programming voltage (<1:4 V) is low. For single-level cell (SLC) operation, the device shows a large resistance window, and 10 8 -cycle endurance. For multi-level cell (MLC) operation, it demonstrates 2-bit/cell storage with the endurance up to 10000 times. The rapid thermal oxidation (RTO) WO x resistance random access memory (RRAM) is very promising for both high-density and embedded memory applications.

The reliability properties of BE-SONOS [1] are extensively studied. BE-SONOS employs a multi-layer O1/N1/O2/N2/O3 stack, where O1/N1/O2 serves as a bandgap engineered tunneling barrier that provides an efficient hole tunneling erase but eliminates the direct tunneling leakage. BE-SONOS can overcome the fundamental limitation of the conventional SONOS, for which fast erase speed and good data retention cannot be simultaneously achieved. In this work, we provide a comprehensive understanding of the reliability of BE-SONOS. Various processes to form the critical O1/N1/O2 barrier, the trapping layer (N2), and the top blocking oxide (O3) are investigated. The results of this work provide design and processing guidelines for optimizing the performance and reliability of BE-SONOS Flash memory devices.