A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

Lai, Erh-Kun; Lue, Hang-Ting; Hsiao, Yi‐Hsuan; Hsieh, Jung-Yu; Lu, Chi-Pin; Wang, Szu-Yu; Yang, Lee‐Wei; Yang, Tahone; Chen, Kuang-Chao; Gong, Jeng; Hsieh, Kuang-Yeu; Liu, Rich; Lu, Chih‐Yuan

doi:10.1109/iedm.2006.346903

Cited by 63 publications

(23 citation statements)

References 4 publications

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“…In order to limit wafer cost, number of vertical layers must be as low as possible and, to compensate this limitation, it is fundamental to use small single cells. Many publications using this array organization have been presented [13,14]. Flexibility and reuse of know-how developed with planar CT cells are probably the reasons to explain the remarkable activity in this area.…”

Section: D Stacked Architecturementioning

confidence: 96%

3D Stacked NAND Flash Memories

Micheloni

Crippa

2016

3D Flash Memories

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In planar Flash memories the most popular memory cell is based on the Floating Gate (FG) technology, whose cross section is shown in Fig. 3.1. Cross section and the associated floating gate model are sketched in Fig. 3.2. Basically, a MOS transistor is built with two overlapping gates: the first one (FG) is completely surrounded by oxide, while the second one forms the Control Gate (CG) terminal. The isolated gate constitutes an excellent "trap" for electrons, enabling long charge retention. The operations used to inject and remove electrons from the isolated gate are called Program and Erase, respectively. These operations modify the threshold voltage V TH of the memory cell, which is, at the end of the day, a MOS transistor. By applying a fixed voltage to the cell's terminals, it is then possible to discriminate two storage levels: when the gate voltage is higher than V TH , the cell is ON ("1"), vice versa it is OFF ("0").To minimize the space on silicon, memory cells are packed together to form a matrix. Depending on how the cells are organized inside the matrix, it is possible to distinguish between NAND and NOR Flash memories. NAND memories are the most widespread in the storage systems; NOR architecture is described in great details in [1].In the NAND string, memory cells are connected in series, in groups of 32, 64, 128, or even 150 [2], as shown in Fig. 3.3. Two select transistors are placed at the edges of the string, to ensure the connection to the source line (through M SL ) and to

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Section: D Stacked Architecturementioning

confidence: 96%

3D Stacked NAND Flash Memories

Micheloni

Crippa

2016

3D Flash Memories

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“…The 3D stackable NAND Flash devices (Jung et al 2006;Lai et al 2006) were demonstrated in 2006, where both single crystal silicon (Jung et al 2006) (by an epitaxial Si process) and poly-silicon TFT (Lai et al 2006) charge-trapping SONOS-type devices were demonstrated, as shown in Fig. 4.1.…”

Section: Brief Comparison Of Various 3d Nand Flash and A General Costmentioning

confidence: 99%

3D NAND Flash Architectures

Lue

2015

Charge-Trapping Non-Volatile Memories

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“…Passive crossbar arrays comprising bipolar memristors at their junctions, have been proposed as convenient geometries to achieve higher density and performance [5][6][7]; they even provide the possibility of having multiple array-layers stacked on top of each other to further augment density and bandwidth [8]. Recently, 20 nm 1 Gb 2-layer 3D ReRAM was implemented [9], thus under optimistic scenarios, 3D ReRAM may continue the density scaling beyond 2D and 3D NAND Flash capabilities [10,11]. However, still there is not enough understanding of the atomic details at device level to be able to project when this will limit the scaling of ReRAM.…”

Section: Introductionmentioning

confidence: 97%