Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory

Wang, Szu-Yu; Lue, Hang-Ting; Lai, Erh-Kun; Yang, Lee‐Wei; Yang, Tahone; Chen, Kuang-Chao; Gong, Jeng; Hsieh, Kuang-Yeu; Liu, Rich; Lu, Chih Yuan

doi:10.1109/relphy.2007.369888

Cited by 13 publications

(9 citation statements)

References 10 publications

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“…However, continuing this phenomenal scaling faces many fundamental obstacles, such as FG interference, geometrical limitation that threatens the gate coupling ratio (GCR), and the few-electron statistical limit. It is forecasted that chargetrapping Flash (CTF) devices [1][2][3] will continue the Flash memory scaling and further propel into 3D-stackable memory devices.…”

Section: Introductionmentioning

confidence: 99%

Performance and reliability optimizations of BE-SONOS NAND Flash using SiON bandgap-tuning tunneling barrier

Liao

Hsieh

Lue

et al. 2010

2010 IEEE International Reliability Physics Symposium

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Bandgap-tunable SiON (oxynitride) tunnel barrier is developed to optimize the performance and reliability of BE-SONOS NAND Flash devices. The HTO O2 layer of the ONO tunnel barrier is replaced by SiON thin films with various refractive index (n) and thickness. We found that with n ≦ 1.72, SiON can provide excellent data retention comparable to conventional BE-SONOS. On the other hand, the erase speed can be greatly improved by using SiON O2 when n > 1.50. We suggest that hole barrier lowering by SiON is the root cause of such erase speed improvement. Our results suggest an optimal 35Å SiON O2 layer with n = 1.63 for the best program/erase speed and data retention performance. Finally, a 75 nm BE-SONOS NAND device is fabricated to validate the performances of this concept.

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Section: Introductionmentioning

confidence: 99%

Performance and reliability optimizations of BE-SONOS NAND Flash using SiON bandgap-tuning tunneling barrier

Liao

Hsieh

Lue

et al. 2010

2010 IEEE International Reliability Physics Symposium

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“…A high work function metal gate suppresses gate injection during E, permitting wider MW [11]. To enable scaling, the SiO 2 tunnel layer is often replaced by a composite multilayered stack [12]- [18]. The engineering of the tunnel dielectric with crested [13], VARIOT [14], symmetric composite [15] tunnel barrier, and double quantum-barrier structure [16] was also found to improve performance.…”

Section: Introductionmentioning

confidence: 99%

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2009

IEEE Trans. Electron Devices

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Abstract-Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap Flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N + ) to Si-rich (Si + ) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant overerase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si + SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si + SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND Flash applications.Index Terms-Charge trap Flash (CTF), program/erase (P/E) window, retention, SANOS, silicon nitride (SiN), SONOS.

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“…Large memory window and better endurance (<0.25-V E-state degradation after 10 4 cycles) have been shown, but retention still remains an important concern. Improved retention may be achieved by using a thicker or engineered tunnel oxide [7], but not without issues of program/erase (P/E) speed reduction or cycling endurance degradation, respectively. Therefore, the [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler–Nordheim Tunneling Program/Erase Operation

Sandhya

Ganguly

Chattar

et al. 2009

IEEE Electron Device Lett.

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Abstract-Silicon-nitride trap layer stoichiometry in charge trap flash (CTF) memory strongly impacts electron and hole trap properties, memory performance, and reliability. Important tradeoffs between program/erase (P/E) levels (memory window), P-and E-state retention loss, and E-state window closure during cycling are shown. Increasing the Si richness of the SiN layer improves memory window, cycling endurance, and E-state retention loss but at the cost of higher P-state retention loss. The choice of SiN stoichiometry to optimize CTF memory performance and reliability is discussed.Index Terms-Charge trap flash (CTF), cycling endurance, program/erase (P/E) window, retention, SANOS, silicon nitride (SiN), SONOS.

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Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory

Cited by 13 publications

References 10 publications

Performance and reliability optimizations of BE-SONOS NAND Flash using SiON bandgap-tuning tunneling barrier

Performance and reliability optimizations of BE-SONOS NAND Flash using SiON bandgap-tuning tunneling barrier

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler–Nordheim Tunneling Program/Erase Operation

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