Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~1011 neuron based) large neural networks.

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Abstract-Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap Flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N + ) to Si-rich (Si + ) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant overerase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si + SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si + SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND Flash applications.Index Terms-Charge trap Flash (CTF), program/erase (P/E) window, retention, SANOS, silicon nitride (SiN), SONOS.

Ultrathin and narrow semiconductor body on insulator allows aggressive scaling of nonvolatile memories for low power, low read/write voltage, high retention, and high density in comparison with bulk devices. We have fabricated memory cells with single-wall carbon nanotubes as channels and gold nanocrystals as charge storage nodes. The devices have large memory windows with low voltage operations and single-electron-controlled drain currents. Coulomb blockade in nanocrystals combined with single charge sensitivity of the nanotube field-effect transistor can potentially enable multilevel operations. Measured retention time is longer than 6200 s at 10 K, but is only about 800 s at room temperature due to the high leakage in evaporated tunnel oxide used in this study. Better dielectric on nanotubes is expected to greatly improve the room-temperature performance for the nanotube memory device.

Abstract-Silicon-nitride trap layer stoichiometry in charge trap flash (CTF) memory strongly impacts electron and hole trap properties, memory performance, and reliability. Important tradeoffs between program/erase (P/E) levels (memory window), P-and E-state retention loss, and E-state window closure during cycling are shown. Increasing the Si richness of the SiN layer improves memory window, cycling endurance, and E-state retention loss but at the cost of higher P-state retention loss. The choice of SiN stoichiometry to optimize CTF memory performance and reliability is discussed.Index Terms-Charge trap flash (CTF), cycling endurance, program/erase (P/E) window, retention, SANOS, silicon nitride (SiN), SONOS.

We report low resistance Ohmic contacts on n-Ge using a thin ZnO interfacial layer (IL) capped with Ti. A 350°C post metallization anneal is used to create oxygen vacancies that dope ZnO heavily n-type (n+). Rectifying Ti/n-Ge contacts become Ohmic with 1000× higher reverse current density after insertion of n+-ZnO IL. Specific resistivity of ∼1.4×10−7 Ω cm2 is demonstrated on epitaxial n+-Ge (2.5×1019 cm−3) layers. Low resistance with ZnO IL can be attributed to (a) low barrier height from Fermi-level unpinning, (b) good conduction band alignment between ZnO and Ge, and (c) thin tunneling barrier due to the n+ doping.

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