Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET

Abstract

Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~1011 neuron based) large neural networks.

Various Threshold Switching Devices for Integrate and Fire Neuron Applications

“…

To implement a SNN using a hardware system, an integrate and fire (I&F) neuron is commonly adopted as a spiking neuron owing to its simplicity. [6] In this regard, volatile thershold switching (TS) devices [7][8][9][10][11] and nonvolatile memory such as resistive random access memory (RRAM) , [12] phase change random access memory (PRAM), [13] ferromagnetic material, [14] and floating body transistor [15] based I&F neurons have been reported to overcome the limitations of conventional CMOS-based neurons. When the membrane potential reaches the threshold voltage of the neuron, the neuron generates spikes to the next synapse layer and resets the membrane potential.

…”

Simulation-Based Ultralow Energy and High-Speed LIF Neuron Using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks

“…So in this work we have replaced the leaky integration function of neuron with the proposed L-BIMOS silicon neuron. One can see that the proposed L-BIMOS silicon neuron requires 0.2 V for firing a spike, which is 60 mV less when compared to previous reported LIF neuron [7] and hence makes the proposed LIF neuron energy efficient. For estimating the energy per spike, we have adopted the following expression [16]:…”

“…Some of them acquires enough energy to produce impact on covalent bond, thereby new electrons and holes are created. The generated electron moves towards drain, and holes are swept into floating body which results in the electrostatic lowering of the potential barrier at the sourcechannel junction and due to which the hole leakage current (I leaky−hole ) starts flowing from the channel region to the source region that defines the "leaky" behavior of the proposed L-BIMOS silicon neuron [7].…”

“…E-mail: (ka-malalok21@gmail.com; jawar@iitp.ac.in). [7], (b) conventional BIMOS [10], and (c) proposed L-BIMOS silicon neuron. supply (avalanche breakdown) voltage requirements of PD-SOI MOSFET silicon neuron to enable impact ionization (or generate excess carriers) for firing a spike consumes significant power and makes it less energy efficient, also slow floating body charging transients of the MOSFET silicon neuron exhibits slow transients behavior of the order of microseconds [9].…”

Neuromorphic Computing with Memristor Crossbar

“…Most NCSs use leaky integrate & fire (LIF) to achieve efficient hardware implementation. As a key to NCS implementation, several neuronal circuits such as floating gate transistor based LIF and silicon neurons are designed . Among them, some types of memristors are exploited as neurons to obtain significant area/power efficiency.…”