Dense crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing massively-parallel and highly energy-efficient neuromorphic computing systems. We first review recent advances in the application of NVM devices to three computing paradigms: spiking neural networks (SNNs), deep neural networks (DNNs), and 'Memcomputing'. In SNNs, NVM synaptic connections are updated by a local learning rule such as spike-timing-dependent-plasticity, a computational approach directly inspired by biology. For DNNs, NVM arrays can represent matrices of synaptic weights, implementing the matrix-vector multiplication needed for algorithms such as backpropagation in an analog yet massively-parallel fashion. This approach could provide significant improvements in power and speed compared to GPU-based DNN training, for applications of commercial significance. We then survey recent research in which different types of NVM devices-including phase change memory, conductive-bridging RAM, filamentary and nonfilamentary RRAM, and other NVMs-have been proposed, either as a synapse or as a neuron, for use within a neuromorphic computing application. The relevant virtues and limitations of these devices are assessed, in terms of properties such as conductance dynamic range, (non)linearity and (a)symmetry of conductance response, retention, endurance, required switching power, and device variability.

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Spin-transfer torque magnetic random access memory (STT-MRAM) is a novel, magnetic memory technology that leverages the base platform established by an existing 100+nm node memory product called MRAM to enable a scalable nonvolatile memory solution for advanced process nodes. STT-MRAM features fast read and write times, small cell sizes of 6F 2 and potentially even smaller, and compatibility with existing DRAM and SRAM architecture with relatively small associated cost added. STT-MRAM is essentially a magnetic multilayer resistive element cell that is fabricated as an additional metal layer on top of conventional CMOS access transistors. In this review we give an overview of the existing STT-MRAM technologies currently in research and development across the world, as well as some specific discussion of results obtained at Grandis and with our foundry partners. We will show that in-plane STT-MRAM technology, particularly the DMTJ design, is a mature technology that meets all conventional requirements for an STT-MRAM cell to be a nonvolatile solution matching DRAM and/or SRAM drive circuitry. Exciting recent developments in perpendicular STT-MRAM also indicate that this type of STT-MRAM technology may reach maturity faster than expected, allowing even smaller cell size and product introduction at smaller nodes.

We demonstrated a proton-based 3-terminal synapse device which shows symmetric conductance change characteristics. Using the optimized device, we successfully confirmed the improved classification accuracy of neural networks for on-chip training.

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To implement a SNN using a hardware system, an integrate and fire (I&F) neuron is commonly adopted as a spiking neuron owing to its simplicity. An I&F neuron integrates the input synaptic current and the membrane potential is charged, as shown in Figure 1a. When the membrane potential reaches the threshold voltage of the neuron, the neuron generates spikes to the next synapse layer and resets the membrane potential. Unfortunately, it is becoming burdensome to use conventional CMOS-based neurons in massive neuromorphic hardware due to their large areas and high power consumption. [6] In this regard, volatile thershold switching (TS) devices [7][8][9][10][11] and nonvolatile memory such as resistive random access memory (RRAM) , [12] phase change random access memory (PRAM), [13] ferromagnetic material, [14] and floating body transistor [15] based I&F neurons have been reported to overcome the limitations of conventional CMOS-based neurons. In nonvolatile memory device based I&F neurons wherein the memory device is used for integrating the input synaptic current, an additional circuit is required to return memory device to its initial state in the reset process of the neuron. However, in a TS-based I&F neuron, due to the volatile voltage hysteric switch characteristic of the TS device, a self-reset process is performed without a reset circuit. Thus, it enables the realization of a compact and low power consumption neuron. Although many TS-based I&F neurons have been studied, only the operations of I&F neuron and their biological plausibility have been reported. However, it is necessary to study and understand the correlation between the switching parameter of a TS device and the neuron characteristics for practical application of TS-based I&F neurons in various SNN-based hardware.Therefore, in this work, we investigated the effect of the switching parameters of the TS devices on the characteristics of TS-based I&F neurons through electrical measurements and computational simulation of three different types of neurons using a NbO 2 -based insulator-to-metal transition device (IMT), [16] a B-Te-based ovonic threshold switching (OTS) device, [17] and a Ag/HfO 2 -based atomic-switching TS device. [18] In addition, we confirmed the feasibility of TS-based neuron by simulating SNN, which converted from analog-based ANN prelearned by backpropagation.This study demonstrates an integrate and fire (I&F) neuron using threshold switching (TS) devices to implement spike-based neuromorphic system. An I&F neuron can be realized using the hysteric voltage switch characteristics of a TS device. To investigate the effects of various TS devices on neuron behavior, neurons are compared using three different types of TS device: NbO 2 -based insulator-to-metal transition (IMT) device, B-Te-based ovonic threshold switching device, and Ag/HfO 2 -based atomic-switching TS device. The results show that the off-state resistance and switching time of the TS devices determine the leaky/nonleaky characteristics and types of activation function ...

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