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We demonstrate a high-performance selection device by utilizing the concept of crested oxide barrier to suppress the sneak current in bipolar resistive memory arrays. Using a TaO(x)/TiO(2)/TaO(x) structure, high current density over 10(7) A cm(-2) and excellent nonlinear characteristics up to 10(4) were successfully demonstrated. On the basis of the defect chemistry and SIMS depth profile result, we found that some Ta atoms gradually diffused into TiO(2) film, and consequently, the energy band of the TiO(2) film was symmetrically bent at the top and bottom TaO(x)/TiO(2) interfaces and modified as a crested oxide barrier. Furthermore, the one selector-one resistor device exhibited significant suppression of the leakage current, indicating excellent selector characteristics.

Multilevel cell (MLC) storage technology is attractive in achieving ultrahigh density memory with low cost. In this letter, we have demonstrated 3-bit per cell storage characteristics in a TaO x -based RRAM. By analyzing the key requirements for MLC operation mainly the switching uniformity and stability of resistance levels, an engineered stack based on thermodynamics in top electrode/(vacancy reservoir/defect control layer)/switching layer/bottom electrode structure was designed. In the optimized stack with ∼10-nm Ta layer incorporated at W/TaO x interface, seven low resistance state levels with same high resistance state were obtained by controlling the switching current down from 30 µA enabling low power 3-bit storage in contrast to the control device which shows 2-bit MLC with resistance saturation. The improved switching and MLC behavior is attributed to the minimized stochastic nature of set/reset operations due to filament confinement by favorable electric field generation and formation of thin but highly conductive filament which is confirmed electrically. Index Terms-Multi-level cell, RRAM, TaO x , vacancy reservoir, defect engineering, dense filament.

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