Pr1–x
Ca
x
MnO3 (PCMO)-based
resistance random access memory
(RRAM) is attractive in large-scale memory and neuromorphic applications
as it is nonfilamentary and area scalable and has multiple resistance
states along with excellent endurance and retention. The PCMO RRAM
exhibits area-scalable resistive switching when in contact with the
reactive electrode. The interface redox reaction-based resistance
switching is observed electrically. Yet, whether the resistance change
occurs near the reactive interface or spread over the entire bulk
is largely debated. Essentially, a two-terminal device is unable to
provide direct evidence of the resistance change region in the PCMO
RRAM. In this paper, we propose and experimentally demonstrate a three-terminal
RRAM (3T-RRAM) device in which a thin third terminal (∼20 nm)
is inserted laterally in close proximity to a typical vertical two-terminal
RRAM device of PCMO thickness ∼80 nm. It is well known that
the reactive interface participates in the resistive switching. However,
using the 3T-RRAM, we demonstrate that the resistance change also
occurs in the region near the inert electrode. We further show that
the resistance measured by T3 is exclusively sensitive to the region
near the inert electrode as opposed to the reactive electrode. Finally,
the highly symmetric space charge limited current (SCLC) characteristics
with polarity at various resistance levels, typical of two-terminal
RRAM, are undisturbed because of the slightly adjacent placement of
the nanoscale inert third terminal while providing resistance change
read sensitivity. It is the first time that an interface redox and
bulk SCLC-based resistance change has been experimentally shown as
correlated and consistent, enabled by the third terminal of the RRAM.
Such a study details a critical understanding of the device which
can enable the design and development of PCMO RRAM for large memory
and neuromorphic computing applications.
The neural network enables efficient solutions for Nondeterministic Polynomial-time (NP) hard problems, which are challenging for conventional von Neumann computing. The hardware implementation, i.e., neuromorphic computing, aspires to enhance this efficiency by custom hardware. Particularly, NP hard graphical constraint optimization problems are solved by a network of stochastic binary neurons to form a Boltzmann Machine (BM). The implementation of stochastic neurons in hardware is a major challenge. In this work, we demonstrate that the high to low resistance switching (set) process of a PrxCa1−xMnO3 (PCMO) based RRAM (Resistive Random Access Memory) is probabilistic. Additionally, the voltage-dependent probability distribution approximates a sigmoid function with 1.35%–3.5% error. Such a sigmoid function is required for a BM. Thus, the Analog Approximate Sigmoid (AAS) stochastic neuron is proposed to solve the maximum cut—an NP hard problem. It is compared with Digital Precision-controlled Sigmoid (DPS) implementation using (a) pure CMOS design and (b) hybrid (RRAM integrated with CMOS). The AAS design solves the problem with 98% accuracy, which is comparable with the DPS design but with 10× area and 4× energy advantage. Thus, ASIC neuro-processors based on novel analog neuromorphic devices based BM are promising for efficiently solving large scale NP hard optimization problems.
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