Reaction-Drift Model for Switching Transients in Pr₀.₇Ca₀.₃MnO₃-Based Resistive RAM

Saraswat, Vivek; Prasad, S.N.; Khanna, Abhishek; Wagh, Ashwin; Bhat, A.; Panwar, Neeraj; Lashkare, Sandip; Ganguly, Udayan

doi:10.1109/ted.2020.3011387

Cited by 12 publications

(11 citation statements)

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“…The increase in temperature further increases the current, creating a positive feedback loop and hence an abrupt rise in current till compliance is reached. As the Joule heating in the device plays an important role in switching, the SET/RESET process has been shown to depend upon ambient temperature conditions. , Further, the reaction-drift model for switching transients in PCMO RRAM quantitatively models the effect of E-field and heat generation on the changing trap density (oxygen vacancies) due to ionic transport …”

Section: Device Operationmentioning

confidence: 99%

Understanding the Region of Resistance Change in Pr_0.7Ca_0.3MnO₃ RRAM

Lashkare

Saraswat

Ganguly

2020

ACS Appl. Electron. Mater.

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Pr1–x Ca x MnO3 (PCMO)-based resistance random access memory (RRAM) is attractive in large-scale memory and neuromorphic applications as it is nonfilamentary and area scalable and has multiple resistance states along with excellent endurance and retention. The PCMO RRAM exhibits area-scalable resistive switching when in contact with the reactive electrode. The interface redox reaction-based resistance switching is observed electrically. Yet, whether the resistance change occurs near the reactive interface or spread over the entire bulk is largely debated. Essentially, a two-terminal device is unable to provide direct evidence of the resistance change region in the PCMO RRAM. In this paper, we propose and experimentally demonstrate a three-terminal RRAM (3T-RRAM) device in which a thin third terminal (∼20 nm) is inserted laterally in close proximity to a typical vertical two-terminal RRAM device of PCMO thickness ∼80 nm. It is well known that the reactive interface participates in the resistive switching. However, using the 3T-RRAM, we demonstrate that the resistance change also occurs in the region near the inert electrode. We further show that the resistance measured by T3 is exclusively sensitive to the region near the inert electrode as opposed to the reactive electrode. Finally, the highly symmetric space charge limited current (SCLC) characteristics with polarity at various resistance levels, typical of two-terminal RRAM, are undisturbed because of the slightly adjacent placement of the nanoscale inert third terminal while providing resistance change read sensitivity. It is the first time that an interface redox and bulk SCLC-based resistance change has been experimentally shown as correlated and consistent, enabled by the third terminal of the RRAM. Such a study details a critical understanding of the device which can enable the design and development of PCMO RRAM for large memory and neuromorphic computing applications.

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Section: Device Operationmentioning

confidence: 99%

Understanding the Region of Resistance Change in Pr_0.7Ca_0.3MnO₃ RRAM

Lashkare

Saraswat

Ganguly

2020

ACS Appl. Electron. Mater.

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“…This increase in the bulk trap concentration related to vacancies causes a nonvolatile resistance change to an HRS during Reset. It has been demonstrated earlier that the Reset operation is a negative feedback between ionic/vacancy motion, current reduction, and temperature reduction . This results in a fast initial vacancy motion when the device temperature is high followed by a long negative feedback tail of gradual Reset.…”

Section: Resultsmentioning

confidence: 92%

“…This drop in bulk traps related to vacancy removal causes a nonvolatile resistance change to LRS during Set. It has been demonstrated earlier that the Set operation is positive feedback between field and temperature assisted ionic/vacancies motion, current increment, and temperature increment . This feedback is only limited by the current limiter external to the device in the form of a compliance or a series resistance.…”

Section: Resultsmentioning

confidence: 96%

“…The ionic/vacancies reaction-drift mechanism for oxygen vacancies related bulk trap switching in W/PCMO/Pt RRAM has been demonstrated earlier. 35 When a negative voltage (Set) is applied to the top W electrode, the vacancies in the bulk travel toward the electrode and combine with the excess oxygen at the reactive electrode. The excess oxygen at the reactive electrode is a consequence of a past Reset operation.…”

Section: ■ Results and Discussionmentioning

confidence: 99%

“…It has been demonstrated earlier that the Set operation is positive feedback between field and temperature assisted ionic/vacancies motion, current increment, and temperature increment. 35 This feedback is only limited by the current limiter external to the device in the form of a compliance or a series resistance. Lower series resistance values limit the current to higher values.…”

Section: ■ Results and Discussionmentioning

confidence: 99%

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Highly Deterministic One-Shot Set–Reset Programming Scheme in PCMO Resistive Random-Access Memory

Phadke

Saraswat

Ganguly

2022

ACS Appl. Electron. Mater.

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Resistive random-access memory (RRAM) devices are very versatile with applications ranging from digital nonvolatile memories to analog synapses and integrate-fire neurons. Recently, RRAM based stochastic neurons have also been proposed for optimization networks that solve NP-hard problems. These applications rely on reliably writing a given conductance state repeatedly. A Pr1–x Ca x MnO3 (PCMO) based RRAM device is a nonfilamentary, bulk switching RRAM which demonstrates low device-to-device variations compared to filamentary RRAMs. However, a low complexity programming scheme to demonstrate low cycle-to-cycle variations (C2CV) as well is needed. In this work, we propose a one-shot Set (initialize) and Reset (program) scheme to experimentally demonstrate low C2CV (<15%) for multiple devices. Compared to one-shot programming on a filamentary device, there is a 2–4× increment in the number of levels that can be stored per device using PCMO RRAM. Further, one-shot programming in PCMO RRAM leads to a 35× (10×) reduction in the number of pulses for 3 (2) bits per device, respectively. This greatly simplifies the memory controller design for these devices compared to any iterative write-verify schemes. This scheme gives a further insight into the self-heating limited Set operation controlled by a series resistor while reinforcing the analog and precise nature of the Reset operation. We studied the impact of the C2CV in programming RRAM-based stochastic neurons on the Max-Cut optimization problem using Boltzmann machines. PCMO RRAM combined with the one-shot programming scheme emerges as the clear choice for a well-controlled RRAM device with minimal peripheral complexity.

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