Unipolar Switching Behaviors of RTO $\hbox{WO}_{X}$  RRAM

Chien, Wei-Ming; Chen, Y.C.; Lai, Erh-Kun; Yao, Y.D.; Lin, Pang; Horng, Shi–Jinn; Gong, Jeng; Chou, T. H.; Lin, Horng–Chih; Chang, Meng‐Fan; Shih, Yung‐Feng; Hsieh, Kuang-Yeu; Liu, R.; Lu, Chih‐Yuan

doi:10.1109/led.2009.2037593

Cited by 104 publications

(44 citation statements)

References 10 publications

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“…Various switching phenomena, such as unipolar and bipolar switching behaviors, are usually explained by different physical mechanisms [4][5][6][7][8]. However, recent reports showed that both unipolar and bipolar switching can co-exist in the same devices [3,[9][10][11], indicating these two behaviors would share the similar physical origin [10][11][12]. In this paper, a unified microscopic principle is proposed to clarify both unipolar and bipolar switching behaviors in metal oxide based RRAM for the first time.…”

Section: Introductionmentioning

confidence: 99%

Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching

Gao

Kang

Chen

et al. 2011

2011 International Electron Devices Meeting

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A unified microscopic principle is proposed to clarify resistive switching behaviors of transition metal oxide based resistive random access memories (RRAM) for the first time. In this unified microscopic principle, both unipolar and bipolar switching characteristics of RRAM are correlated with the distribution of localized oxygen vacancies in the oxide switching layer, which is governed by the generation and recombination with dissociative oxygen ions. Based on the proposed microscopic principle, an atomistic simulation method is developed to evaluate critical memory performance, and successfully conduct the device optimization. The experimental data are well in line with the developed simulation method.

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Section: Introductionmentioning

confidence: 99%

Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching

Gao

Kang

Chen

et al. 2011

2011 International Electron Devices Meeting

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“…In particular, the research in the areas of transition metal oxide (TMO) based RRAM devices has gathered significant attention due to their ease in the integration with CMOS technology. [1][2][3][4][5][6] However, in spite of significant progress, there is still a critical gap in the knowledge base pertaining to our lack of understanding on the fundamental switching and data storage mechanisms in these devices. In this letter, we report a systematic study of the charge transport mechanism in virgin resistance state (VRS), low resistance state (LRS), and high resistance state (HRS) of RRAM devices consisting of Ru/ HfO 2 /TiO x /Ru stacks.…”

mentioning

confidence: 99%

Switching dynamics and charge transport studies of resistive random access memory devices

Long¹,

Li²,

Mandal³

et al. 2012

Applied Physics Letters

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We report the switching dynamics and charge transport studies on Ru/HfO2/TiOx/Ru resistive random access memory devices in low resistance state (LRS), high resistance state (HRS), and virgin resistance state (VRS). The charge transport in LRS is governed by Ohmic conduction of electrons through local filamentary paths while it is governed by a combination of Frenkel-Poole emission and trap assisted tunneling process in HRS and VRS. The area of the filament in LRS is extracted and related to the compliance current. The thickness of the re-oxidized filament is extracted and related to the reset voltage in HRS. The energy consumed during the reset process was analyzed on the time-scale to experimentally demonstrate joule-heating mediated oxidation dynamics of filament during device reset.

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“…After an initial forming step at ~ -2.2V, the device can be reset and set at +1.8V and -1.2V, as shown in Fig.2. Figure 3 shows that the RESET and SET voltages are independent of device size, suggesting that the switching mechanism is dominated by filament formation/disruption [4][5]. On the other hand, the switching current for the 40nm device is drastically reduced, with also high initial resistance (Fig.4).…”

Section: Characteristics Of 40nm Wo X Devicementioning

confidence: 99%

Multi-level 40nm WO<inf>X</inf> resistive memory with excellent reliability

Chien

Lee

et al. 2011

2011 International Electron Devices Meeting

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Fig.1 The cross sectional TEM image of the 40nm WOX ReRAM cell. The ring of TiNOX produced during RTO of W plug is non-conducting. Fig.3 RESET and SET voltages for WOX devices of various size. The switching voltages are independent of device size, an indication of filament forming/rupturing mechanism [4-5].Fig.4 RESET/SET current and initial resistance for various WOX devices.Switching current for 40nm device decreases drastically, while the initial state resistance increases as device scales. The smaller devices are more power efficient. Fig.2 Operation of the 40nm WOX device. A negative forming pulse is used to obtain the first SET state. Then the cell can be switched in bipolar operation: Positive pulse for RESET, and negative pulse for SET. Abstract40nm WO X ReRAM has several unique characteristics that are very favorable for MLC application. (1) Although the resistance has strong temperature dependence (as for all ReRAM's) the J-V characteristics can be accurately described, thus all MLC levels are easily modeled. (2) The device is immune to over-erase, thus allow fast MLC programming. (3) The programming is self-converging (as Flash memories) and is independent of history. Thus an algorithm similar to ISPP (Incremental Step Pulse Programming), commonly used by MLC NAND flash, is designed to achieve accurate MLC states. Consequently, fast 50ns switching, 2-bit/cell and 3-bit/cell MLC states with good cycling characteristics and low read disturbance (> 10 10 ) is achieved.

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Unipolar Switching Behaviors of RTO $\hbox{WO}_{X}$ RRAM

Cited by 104 publications

References 10 publications

Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching

Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching

Switching dynamics and charge transport studies of resistive random access memory devices

Multi-level 40nm WO<inf>X</inf> resistive memory with excellent reliability

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