A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRAM technology fully compatible with high performance logic with high-κ metal gate access transistor and high-κ node dielectric for the deep trench storage capacitor.We also describe the technology advancements required to scale the deep trench as well as the access transistor for optimal cell retention and performance. A clear scaling path is seen for the 22nm technology node.

Hydrogenated “diamondlike” carbon (DLC) is a potential candidate as a low k material for the back end interconnect (BEOL) dielectric for VLSI chips. The DLC material is an attractive dielectric due to its isotropic properties and the ability to deposit the films by CVD techniques, such as PECVD or HDP systems. Under suitable preparation conditions such materials can reach dielectric constant values below 2.8, even as low as 2.4. While the as-deposited films are not stable to exposure to subsequent processing temperatures of about 400 C, it appears that they can be stabilized, in terms of dimensional stability and material loss, by an initial anneal.The integration of DLC films in the BEOL structure further requires good adhesion with the materials in contact with the DLC dielectric, such as silicon nitride or silicon oxide, and liner metallurgy. As the potential application of the DLC films will be in Cu based damascene structures the behavior of the films under CMP conditions is also important.The talk will discuss the evaluation of DLC films and of integration issues such as adhesion under processing conditions, patterning, CMP behavior. Blanket and patterned structures built with DLC films will be presented.

This paper presents for the first time a full 32nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (A VT ) improvement (A VT~2 .8mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent Static Noise Margin (SNM) of 213mV has been achieved at low voltage for a high density 0.157um 2 SRAM cell. Hierarchical BEOL based on Extreme Low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125ºC.

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As technology progresses, the need for thinner Cu diffusion barrier caps is becoming more important, and it is advantageous if these barriers have low dielectric constants (κ). Towards this end, we characterized Cu penetration in several thin (35 nm to 70 nm) dielectrics, including silicon nitrides, silicon oxynitrides, an amorphous hydrogenated carbon film, and a methyl silsesquioxane layer. Metal Insulator Silicon (MIS) structures were used as the test vehicle. The barrier dielectrics were deposited on 100 nm thermal oxide which was grown on 2 Ω-cm, n-type Si wafers. After the deposition of 50 nm TEOS capping layers, both Al and Cu dots were evaporated on each wafer through a mask. Both Al and Cu dot samples were stressed at +2.7 MV/cm at 300°C for 10 minutes. For Cu dots, the applied stress pushed Cu ions into the dielectric stack. Stressing Al dots characterized the effects of the stress on the dielectric stacks and the quantity of Na ions in the films. Since C-V shifts are subject to stress-related instabilities in the interfaces as well as within the dielectrics themselves, triangular voltage sweep (TVS) was used after the applied stress to measure the concentration of Cu which reached the underlying thermal oxide film. The sensitivity of the TVS test with the structures used is about 5×109/cm2. Secondary ion mass spectroscopy (SIMS) analyses were performed on some of these samples to verify the electrical results.