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Boron diffusion in ion-implanted and annealed single-crystal and amorphized Si is compared to determine the effect of amorphization on the initial transient boron motion reported for single crystal. The boron was implanted at 20 keV and at doses of 1×1015 and 3×1015cm−2. The Si was either preamorphized or postamorphized to a depth of 320 nm by implantation of Si ions at three different energies. In the amorphized samples the entire boron profile was always contained within this distance. The samples were annealed by furnace or rapid thermal annealing to 900–1100 °C with or without a preanneal at 600 °C. The initial rapid diffusion transient in the tail region of the boron profile was observed in all the crystal samples. This transient was totally absent in the amorphized samples. This is manifest by careful comparison of boron concentration profiles determined by secondary ion mass spectrometry of single-crystal and amorphized samples after annealing. For anneals where significant motion occurs, the profiles of the amorphized samples could be fit with a computational model that did not include anomalous transient effects. It is proposed that excess interstitials cause the transient diffusion in the case of the crystalline samples. The source of interstitials is believed to be provided by the thermal dissolution of small clusters that are formed by the implantation process. They exist for only a short time, during which they enhance the boron diffusion. Since there is no enhanced diffusion in the amorphous region that regrows to single crystal, apparently interstitial clusters are neither produced by nor do they survive the regrowth process in that region. In addition, the interstitials generated by the damage beyond the amorphous-crystalline boundary are prevented from entering the regrown region by the dislocation loops formed at that boundary which act as a sink consuming the interstitials diffusing toward the surface.

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A variety of diamondlike carbon (DLC) materials were investigated for their potential applications as low-k dielectrics for the back end of the line (BEOL) interconnect structures in ULSI circuits. Hydrogenated DLC and fluorine containing DLC (FDLC) were studied as a low-k interlevel and intralevel dielectrics (ILD), while silicon containing DLC (SiDLC) was studied as a potential low-k etch stop material between adjacent DLC based ILD layers, which can be patterned by oxygen-based plasma etchingIt was found that the dielectric constant (k) of the DLC films can be varied between >3.3 and 2.7 by changing the deposition conditions. The thermal stability of these DLC films was found to be correlated to the values of the dielectric constant, decreasing with decreasing k. While DLC films having dielectric constants k>3.3 appeared to be stable to anneals of 4 hours at 400 °C in He, a film having a dielectric constant of 2.7 was not, losing more than half of its thickness upon exposure to the same anneal. The stresses in the DLC films were found to decrease with decreasing dielectric constant, from 700 MPa to about 250 MPa. FDLC films characterized by a dielectric constant of about 2.8 were found to have similar thermal stability as DLC films with k >3.3. The thermally stable FDLC films have internal stresses <300 MPa and are thus promising candidates as a low-k ILD.For the range of Si contents examined (0-9% C replacement by Si), SiDLC films with a Si content of around 5% appear to provide an effective etch-stop for oxygen RIE of DLC or FDLC films, while retaining desirable electrical characteristics. These films showed a steady state DLC/SiDLC etch rate ratio of about 17, and a dielectric constant only about 30% higher than the 3.3 of DLC.

The flatbandhhreshold voltages (VJV,) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO2 at poly-Si deposition temperatures is identified as the root cause for the poor VJV, control. No improvement in V, control is obtained by engineering physically closed Si3N4 barrier layers on Hf02. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large VnJV, shifts are observed with HfO,. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using AI203 cap layers on silicates.