Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates

Abstract

The flatbandhhreshold voltages (VJV,) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO2 at poly-Si deposition temperatures is identified as the root cause for the poor VJV, control. No improvement in V, control is obtained by engineering physically closed Si3N4 barrier layers on Hf02. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large VnJV, shifts are observed with HfO,. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using AI203 cap layers on silicates.

Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges

“…The introduction of Si or N into the Hf-based layer has a limited impact on V t /V fb . As expected, when utilizing HfSiO with increasing Si content, V fb gradually approaches the value observed with SiO 2 (Figure 4, inset) [67,[69][70][71][72]. However, in order to bring V t to within less than 0.3 V from the target value, Hf contents below ;20% are required.…”

“…We have tested whether tuning of processing details, in particular choice of dopant, method of doping (implant vs. in situ doping with CVD precursors), and thermal processing, can help control V t . To this end, the V fb /V t shifts were measured after such critical gate-stack fabrication steps [70]. Measurements even with undoped and unactivated polySi gates were made possible by recording electrical data at elevated device temperatures (up to 2008C) in order to ensure sufficient conductivity.…”

“…Si and N are not candidate species causing the p-FET V t problem, since N-free HfO 2 /SiO 2 stacks suffer from it, and since the intentional introduction of Si partially alleviates the issue (see below). The impact of gate dopants was excluded by the careful experimental studies discussed above [70].…”

Modeling of the effective work function instability in metal/high-κ dielectric stacks

“…However, this result contradicts reports that thin capping layers do not correct the V fb shift, 24 and should not influence the charge build up. Increasing the top oxide thickness or reducing the IL thickness has the same effect on ⌬V fb .…”

MOS Characteristics of Substituted Al Gate on High-<tex>$kappa$</tex>Dielectric

“…However, it is still not easy to achieve a work function low enough for bulk nMOSFET using FUSI metal gate on high-dielectric. The Si-Hf reaction at the interface between polysilicon and Hf-based dielectric may also complicate the work function adjustment in FUSI gate [9]. In this letter, we propose and demonstrate substituted aluminum (SA) gate on high-dielectric as an alternative way of forming a metal gate.…”